Abstract: A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and “stitches” them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver.

Abstract: An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.

Abstract: A memory system comprising memory modules including memory chips including integrated switching circuits. A memory controller coupled to the memory modules is configured to initiate memory accesses. When a switching circuit within a memory chip detects the memory access, the switching circuit routes the access to another memory module if the access is not directed to a memory chip of the receiving memory module, or processes the access locally if the access is directed to a memory chip of the receiving memory module. The memory controller and memory modules are coupled via bi-directional serial links. Each memory module may include multiple switching circuits, each of which may be coupled to fewer than all of the memory chips within the memory module. Switching circuits further include circuitry configured to de-serialize data prior to conveyance to a memory chip, and serialize data received from a DRAM chip prior to transmitting the received data.

Abstract: A method, apparatus, and system for minimizing ringing in a high speed channel between a transmitter and a receiver in a circuit, including a component for initializing an n-tap equalization filter. The n-tap equalization filter includes numerous taps, each associated with each of numerous jitter pulses received from the transmitter at the receiver and over the channel. Many of the jitter pulses are greater than two. Further, each tap occurs at a time-domain point related to a time of a corresponding jitter pulse included within the numerous jitter pulses. Moreover, a component for applying the n-tap equalization filter to a subsequent signal sent over the channel is also included.

Abstract: A memory system comprising memory modules including memory chips stacked with switching circuits. A memory controller coupled to the memory modules is configured to initiate memory accesses. When a stacked switching circuit detects the memory access, the switching circuit routes the access to another memory module if the access is not directed to a memory chip of the receiving memory module, or processes the access locally if the access is directed to a memory chip of the receiving memory module. The memory controller and memory modules are coupled via bi-directional serial links. Each memory module may include multiple stacked switching circuits, each of which may be coupled to fewer than all of the memory chips within the memory module. Switching circuits further include circuitry configured to de-serialize data prior to conveyance to a memory chip, and serialize data received from a DRAM chip prior to transmitting the received data.

Abstract: An apparatus and methods for recovering a clock and a data stream from a source synchronous input data stream are disclosed. The apparatus comprises a filter, a decision feedback equalizer (DFE), a phase error detector, and a clock generator. The input data stream is coupled to the filter and the DFE. The DFE synchronizes the input data stream to a clock generated by the clock generator. A filter output and a DFE output are each coupled to the phase error detector. During an initialization period, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the filter output and during a period of steady-state operation, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the DFE output. The output of the DFE comprises a recovered data stream.

Abstract: A computer system which may allow a centerplaneless design. The computer system may include various client circuit boards including processor circuit boards, memory circuit boards and switch circuit boards. The processor circuit boards may each include at least one processor, while the memory circuit boards may each include memory which is accessible by each processor. The switch circuit boards may include a plurality of detachable connectors for interconnecting each of the processor circuit boards to each of the memory circuit boards. At least one of the switch circuit boards may convey redundant memory access information. Each of the boards may be hot swappable.

Abstract: A data communications system is disclosed. The data communications system comprises two clock domains. A first clock domain includes a transmitter and a first clock signal. A second clock domain includes a receiver and a second clock signal. The transmitter conveys the first clock signal and a data signal to the receiver. The receiver: (a) counts a first number of transitions of the second clock signal in response to detecting a transition of the first clock signal; (b) maintains a first count of the number of transitions of the second clock signal; (c) samples the data signal and maintains a second count of the number of transitions of the second clock signal in response to detecting the first count equals a first pre-determined value; and (d) samples the data signal and resets the second count in response to detecting the second count equals a second pre-determined value.

Abstract: A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data utilizing a corresponding received source synchronous clock signal, and transmit the recovered data and a corresponding clock signal in a source synchronous manner. In one embodiment, the device is configured to operate as a repeater without benefit of an internal clock signal. In addition, the device may be configured to remove data jitter and renew or restore amplitude to attenuated signals prior to retransmission.

Abstract: An apparatus and method for distributing multiple clock signals to multiple devices using an encoded clock signal is provided. A source clock signal can be encoded to result in an encoded system clock. The encoded system clock can be distributed to multiple devices in a computer system. The devices can decode the encoded system clock signal to generate a system clock signal and a global clock signal. The system clock signal and the global clock signal can then be distributed to their respective clock loads on each device. In certain embodiments, additional information, such as state information, can be encoded into the encoded system clock. A device can be configured to decode the additional information and can alter its state accordingly.

Abstract: Circuit board orientation in a computer system. A system includes a first set of circuit boards and a second set of circuit boards. The first set of circuit boards may be mated via a first and second set of connectors to the second set of circuit boards such that the first set of circuit boards is oriented substantially orthogonal with respect to the second set of circuit boards. Each of the boards may be accessible and hot swappable.

Abstract: An optical transmitter for transmitting a first output data signal and a second output data signal, the optical transmitter comprising: a phase-locked-loop, the phase-locked-loop operable to receive a reference clock signal; a clock-recovery circuit, the clock-recovery circuit coupled to the phase-locked-loop, the clock-recovery circuit operable to receive a first input data signal; a latch-decision circuit, the latch-decision circuit coupled to the clock-recovery circuit; a latch, the latch coupled to the latch-decision circuit, the latch operable to receive the first input data signal and the second input data signal; a first electro-optical converter, the first electro-optical converter coupled to the latch, the first electro-optical converter operable to transmit the first output data signal; and a second electro-optical converter, the second electro-optical converter coupled to the latch, the second electro-optical converter operable to transmit the second output data signal.

Abstract: A memory subsystem including memory modules having multiple banks. A memory subsystem includes a memory controller and a plurality of memory modules. The plurality of memory modules may be coupled to the memory controller by a memory interconnect having a data path including a plurality of data bits. Each of the plurality of memory modules includes a circuit board and a plurality of memory chips mounted to the circuit board. The circuit board includes a connector edge for connection to the memory interconnect. Each of the plurality of memory chips may be configured to store data in a plurality of storage locations. Each of the plurality of memory modules may be coupled to a respective mutually exclusive subset of the plurality of data bits.

Abstract: A computer system employing redundant power distribution. A computer system includes power distribution boards arranged to distribute power such that the computer system may continue to operate if there is any single point of power failure. The computer system includes a first plurality of circuit boards, a plurality of switch circuit boards and a first and second power distribution board. The plurality of switch circuit boards may be coupled to the first plurality of circuit boards and may convey address and data information between the first plurality of circuit boards. The first power distribution board and the second power distribution board may be coupled to independently distribute power to each of the first plurality of circuit boards. At least two of the first plurality of circuit boards may be coupled to independently distribute power to each of the plurality of switch circuit boards.

Abstract: An electrical connector for conveying signals between two circuit boards includes a first connector portion including a first array of board contacts for connection to a first corresponding footprint on a first circuit board. The connector also includes a second connector portion including a second array of board contacts for connection to a second corresponding footprint on a second circuit board. The signals include a plurality of signal groups each including a different plurality of related signals. Each of the signal groups is assigned to a grouping of related board contacts of the first array and to a corresponding grouping of related board contacts of the second array. When the first connector portion and the second connector portion are mated, each grouping of board contacts of the first array is electrically coupled to the corresponding grouping of board contacts in a transposed location in the second array.

Abstract: An electrical connector for conveying signals between two circuit boards. An electrical connector includes a first connector portion including a first array of board contacts for connection to a first corresponding footprint on a first circuit board. The connector also includes a second connector portion including a second array of board contacts for connection to a second corresponding footprint on a second circuit board. The signals include a plurality of signal groups each including a different plurality of related signals. Each of the signal groups is assigned to a grouping of related board contacts of the first array and to a corresponding grouping of related board contacts of the second array. When the first connector portion and the second connector portion are mated, each grouping of board contacts of the first array is electrically coupled to the corresponding grouping of board contacts in a transposed location in the second array.

Abstract: A memory system including independent power for each memory module. The memory system includes a plurality of memory modules each including a plurality of memory chips configured to store data. The memory system further includes a power conversion unit coupled to provide power to each of the plurality of memory modules via a respective power conduit. Each of the respective power conduits is electrically isolated from each other power conduit.

Abstract: A computer system employing redundant cooling fans. A system includes a first and a second array of circuit boards and a first and a second cooling fan. The two arrays of circuit boards are positioned such that the first array of circuit boards is substantially perpendicular to the second array of circuit boards. The first fan is positioned close to the first array of circuit boards and the second fan is positioned close to the second array of circuit boards. The first fan is positioned to force intake air across the first and the second arrays of circuit boards and the second fan is positioned to exhaust the forced intake air after it passes over the second array of circuit boards. Each of the fans may be hot swappable.

Abstract: A memory subsystem including memory modules having multiple banks. A memory subsystem includes a memory controller and a plurality of memory modules. The plurality of memory modules may be coupled to the memory controller by a memory interconnect having a data path including a plurality of data bits. Each of the plurality of memory modules includes a circuit board and a plurality of memory chips mounted to the circuit board. The circuit board includes a connector edge for connection to the memory interconnect. Each of the plurality of memory chips may be configured to store data in a plurality of storage locations. Each of the plurality of memory modules may be coupled to a respective mutually exclusive subset of the plurality of data bits.

Abstract: A system and method for switching between input clock signals from different clock sources without losing lock by providing a supplemental correction signal to the loop filter in a phase locked loop (PLL) circuit. The phase detector includes a supplemental correction pulse generator configured to offset, at least partially, the effects of losing an input clock signal from a first clock source failure. The phase detector is coupled to receive the input clock signal and a feedback signal. The phase detector outputs a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The loop filter is coupled to receive the phase error signal and to output an error correction signal. A voltage controlled oscillator is coupled to receive the error correction signal and to generate the output signal of the PLL, with the feedback signal indicative of the output signal. Switching logic is coupled to monitor the input clock signal from the first clock source for a failure.