Abstract: A high-performance computing system, method, and storage medium manage accesses to multiple memory modules of a computing node, the modules having different access latencies. The node allocates its resources into pools according to pre-determined memory access criteria. When another computing node requests a memory access, the node determines whether the request satisfies any of the criteria. If so, the associated pool of resources is selected for servicing the request; if not, a default pool is selected. The node then services the request if the pool of resources is sufficient. Otherwise, various error handling processes are performed. Each memory access criterion may relate to a memory address range assigned to a memory module, a type of request, a relationship between the nodes, a configuration of the requesting node, or a combination of these.

Abstract: Multi-node, multi-socket computer systems and methods provide packet tunneling between processor nodes without going through a node controller link. On receiving a packet, the destination node identifier (NID) is examined, and if it is not same as the source socket, then the packet request address is examined. If it is determined that the packet is not for a remote connected socket, then the packet's destination NID and source socket NID are replaced along with recalculated data protection information. The modified packet is then sent to the destination socket over another processor interconnect path.

Abstract: Methods and systems are provided for circuits. One method is for increasing device threshold voltage distribution of a plurality of devices of a circuit. The method includes adjusting a device threshold voltage of the plurality of devices by different amounts; and selecting a subset of the plurality of devices with adjusted device threshold voltage by a device selection module for performing a function associated with the circuit. In one aspect, a system for device threshold voltage adjustment is provided. The system includes a sensor module for sensing one or more of temperature and voltage values of a die having a plurality of devices for a circuit; and a threshold temperature and voltage compensation module for receiving an input value from the sensor module to compensate variation in a device threshold voltage caused by changes of one or more of temperature and voltage of the die.

Abstract: A node controller for a first processor socket group may include a node memory storing a coherence directory and logic. Logic may cause the node controller to: receive a memory operation request directly from a second processor socket group, follow a coherence protocol based on the memory operation request and the coherence directory and directly access a socket group memory of the first processor socket group based on the request.

Abstract: A transmitting device can compress a packet prior to transmitting the packet to a receiving device, which then decompresses the packet. The packet can be combined into a single combined packet with other packets within a transmission queue of the same type and that refer to consecutive memory block addresses. A header of the packet can be replaced with a reduced-size header including a sequence number and a flag indicating the header has been replaced with the reduced-size header, if the packet has a consecutive memory block address to that of the most recently transmitted packet. A payload of the packet may also be compressed.

Abstract: A first node controller may include logic to direct the first node controller to: receive a noncoherent inter-processor communication from a source processor, remap the noncoherent inter-processor communication to a local address space of a destination processor and transmit the noncoherent inter-processor communication directly to a second node controller of the destination processor using an interconnect interface that also carries coherent communications.

Abstract: A first node controller may include logic to direct the first node controller to: receive a noncoherent inter-processor communication from a source processor, remap the noncoherent inter-processor communication to a local address space of a destination processor and transmit the noncoherent inter-processor communication directly to a second node controller of the destination processor using an interconnect interface that also carries coherent communications.

Abstract: A transmitting device generates a nominally unguaranteed error-detection code for each sub-data packet of a data packet, and a nominally guaranteed error-detection code for the data packet. The transmitting device transmits to a receiving device the data packet including the sub-data packets thereof, the nominally guaranteed error detection codes for the sub-data packets, and the nominally guaranteed error-detection code for the data packet. For each sub-data packet, the receiving device uses the nominally unguaranteed error-detection code for each sub-data packet to determine whether the sub-data packet is erroneous. In response to determining that no sub-data packet is erroneous, the receiving device uses the nominally guaranteed error-detection code for the data packet to determine whether the data packet is erroneous.

Abstract: A node controller to manage access to and provide responses from a remote memory for a plurality of processor nodes. A learning block monitors requests to a given data block in the remote memory and monitors parameters associated with the requests. The learning block updates a respective weighting value for each of the parameters associated with the requests to the given data block. Event detection circuitry stores the parameters and the weighting values for each of the parameters associated with an address for the given data block to determine a subsequent memory action for the prospective data block in the remote memory.

Abstract: A system includes a volatile memory to store data and a memory controller to manage the data in the volatile memory. The memory controller includes an inner code generator to generate a respective inner correction code for each of a plurality of blocks of the data in the volatile memory. An outer code generator generates an outer correction code based on the plurality of blocks of the data. The memory controller updates the outer correction code as part of a refresh to the plurality of blocks of the data in the volatile memory.

Abstract: A system, method, and storage medium provide dynamic, packet-based adaptive forward error correction over a lossy bidirectional data communication medium that couples a transmitting device to a receiving device. The transmitting device repeatedly transmits encoded data packets formed by applying, to unencoded data, a forward error correction (FEC) algorithm having a level N that indicates a number of correctable errors. The receiving device attempts to decode the encoded data packets using the FEC algorithm, requesting retransmission of a packet if there are too many errors to correct. The transmitting device decreases the level N when it does not receive such a request within a given duration. By contrast, the transmitting device increases the level N when it receives a sequence of such requests having a threshold length, each request being received less than the given duration after the previous request.

Abstract: A high-performance computing system, method, and storage medium manage accesses to multiple memory modules of a computing node, the modules having different access latencies. The node allocates its resources into pools according to pre-determined memory access criteria. When another computing node requests a memory access, the node determines whether the request satisfies any of the criteria. If so, the associated pool of resources is selected for servicing the request; if not, a default pool is selected. The node then services the request if the pool of resources is sufficient. Otherwise, various error handling processes are performed. Each memory access criterion may relate to a memory address range assigned to a memory module, a type of request, a relationship between the nodes, a configuration of the requesting node, or a combination of these.

Abstract: A system, method, and storage medium provide dynamic, packet-based adaptive forward error correction over a lossy bidirectional data communication medium that couples a transmitting device to a receiving device. The transmitting device repeatedly transmits encoded data packets formed by applying, to unencoded data, a forward error correction (FEC) algorithm having a level N that indicates a number of correctable errors. The receiving device attempts to decode the encoded data packets using the FEC algorithm, requesting retransmission of a packet if there are too many errors to correct. The transmitting device decreases the level N when it does not receive such a request within a given duration. By contrast, the transmitting device increases the level N when it receives a sequence of such requests having a threshold length, each request being received less than the given duration after the previous request.

Abstract: Various systems and methods may aggregate content from one or more poll results database/sources, social media platforms, content sites, and/or other sources. For polling data, each category of results may correspond to direct responses to polling questions. For example, a question may be posed to respondents “Do you have a favorable or unfavorable impression of <Entity>?” in which “<Entity>” corresponds to an entity for which a brand score is being generated. The responses may include the categories such as: “Very Favorable,” “Somewhat Favorable,” “Somewhat Unfavorable,” “Very Unfavorable,” “Never Heard Of,” “Heard Of, but No Opinion.” For non-polling data, the system may parse the content (e.g., words or phrases, graphics such as “emoji”, comments, etc.) to categorize the non-polling data into one of the above categories, which may correspond to a polling category. Brand scores may be generated based on the polling data and/or the non-polling data.

Abstract: In one aspect a system is provided. The system a plurality of flash compare modules to output a set of unordered output signals based on an analog input signal; a plurality of device selection modules that receive the unordered output signals and generate ordered signals representing the analog input; and a temperature and voltage compensation module for receiving one or more of temperature and voltage signals from at least a temperature and voltage sensor module that senses one or more of temperature and voltage values that are used to compensate for changes in output signals caused by changes in one or more of die temperature and core voltage.

Abstract: A memory device may include a memory unit having multiple channel structures connected to a common source and drain in parallel. The memory unit can include floating gate structures including control gates connected to word lines and charge trap layers to store charge to form tiered floating gate memory cells. In some embodiments, rows and columns of memory units can be connected to form a three dimensional memory device. A method of fabricating a memory unit having tiered channel structures utilizing common source and drain elements and 3D memory device utilizing rows and columns of memory units having multiple channel structures connected to the common source and drain elements in parallel is disclosed.

Abstract: Systems and methods for encrypted processing are provided. For example, an apparatus for encrypted processing includes: an input interface adapted to receive input from a device; an encrypted processor connected to the input interface; a program store control connected to the encrypted processor, the program store control controlling use of and access to at least two program stores, where at least one program store acts as a primary program store and at least one program store acts as a back-up program store; and an output interface connected to the encrypted processor for outputting at least one of commands or data; where the encrypted processor is programmed to: receive and validate a request; determine whether a valid request is a program update request for a first program; and initiate a lock mechanism into a locked state.

Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.

Abstract: In one aspect a system is provided. The system a plurality of flash compare modules to output a set of unordered output signals based on an analog input signal; a plurality of device selection modules that receive the unordered output signals and generate ordered signals representing the analog input; and a temperature and voltage compensation module for receiving one or more of temperature and voltage signals from at least a temperature and voltage sensor module that senses one or more of temperature and voltage values that are used to compensate for changes in output signals caused by changes in one or more of die temperature and core voltage.

Abstract: Systems and methods may analyze polling results and generate polling results outputs based on respondent characteristics, generating slide documents using one or more polling results outputs, saving and sharing poll results outputs, and performing trending analytics based on polls. A poll results output may be dynamically generated and modified by monitoring user-provided filter parameters. The system may overlay secondary information related to poll responses to augment the customizable view of the poll results. The poll results output may be starred by a user so that the user may later access the poll results. The poll results output may be shared by the user through social networking platforms, content sites, and email and other communication channels. The system may perform trending analytics on the polling results in order to detect and display trends related to polls.