Abstract: The present disclosure provides a neuromorphic device and a method of driving the same. The neuromorphic device of the present disclosure includes a channel, the magnetization direction of which is changed as a plurality of data is integrated, first and second magnetization regulators formed on both ends of the channel and responsible for changing the magnetization direction of the channel according to a plurality of input data, and a controller formed on the channel between the first and second magnetization regulators and responsible for firing data equal to or greater than a critical value integrated in the channel.

Abstract: A memory device contains lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode, which are formed on a substrate in a laminated manner. In the memory device, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.

Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic (SyAF) layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, SyAF layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the SyAF layers to grow in the FCC (111) direction.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.

Abstract: A memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. The lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Abstract: The present invention relates to a memory device including a substrate and a lower electrode, buffer layer, seed layer, Magnetic Tunnel Junction (MTJ), capping layer, synthetic antiferromagnetic layer, and upper electrode formed on the substrate.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.

Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic (SyAF) layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, SyAF layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the SyAF layers to grow in the FCC (111) direction.

Abstract: The present disclosure provides a neuromorphic device and a method of driving the same. The neuromorphic device of the present disclosure includes a channel, the magnetization direction of which is changed as a plurality of data is integrated, first and second magnetization regulators formed on both ends of the channel and responsible for changing the magnetization direction of the channel according to a plurality of input data, and a controller formed on the channel between the first and second magnetization regulators and responsible for firing data equal to or greater than a critical value integrated in the channel.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic exchange diamagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic exchange diamagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic exchange diamagnetic layers to grow in the FCC (111) direction.

Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic exchange diamagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic exchange diamagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic exchange diamagnetic layers to grow in the FCC (111) direction.

Abstract: The present invention relates to a memory device including a substrate and a lower electrode, buffer layer, seed layer, Magnetic Tunnel Junction (MTJ), capping layer, synthetic exchange diamagnetic layer, and upper electrode formed on the substrate.

Abstract: The present invention suggests a substrate manufacturing method and a manufacturing method of a semiconductor device comprising: providing a SOI structure having an insulation layer and a silicon layer laminated on a substrate; laminating to form a silicon germanium layer and a capping silicon layer on the SOI structure; implementing oxidation process at two or more temperatures and heat treatment process at least once during the oxidation process to form a germanium cohesion layer and a silicon dioxide layer; and removing the silicon dioxide layer.