Abstract: A method for fabricating an array of front ends for an array of packaged electronic components that each comprise: an electrical element packaged within a package comprising a front part of a package comprising an inner section with a cavity therein opposite the resonator defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads that are coupleable in a ‘flip chip’ configuration to a circuit board; the method comprising the stages of: i. Obtaining a carrier substrate having an active membrane layer attached thereto by its rear surface, with a front electrode on the front surface of the active membrane layer; ii.

Abstract: A packaged electronic component comprising: an electronic component housed within a package comprising a front part of a package comprising an inner section with a front cavity therein opposite the electronic component defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads adapted to couple the package in a flip chip configuration to a circuit board.

Abstract: The surface of the MEMS piezoelectric transducer that optimizes the capacitor shape of the present application is covered with m groups of capacitor (101, 102, 103, 104, 109), m being a natural number ?2. When the MEMS piezoelectric transducer is loaded with a certain load, a stress of a region covered by any one of a first group of capacitors>a stress of a region covered by any one of a second group of capacitors> . . . >a stress of a region covered by any one of a (m?1)th group of capacitors>a stress of a region covered by any one of a mth group of capacitors. Capacitors of the same group are connected in series and/or in parallel; capacitors of different groups are connected in series. The present application performs optimization design to the shape, position and number of the capacitor based on the stress distribution of the MEMS piezoelectric transducer when a certain load is loaded.

Abstract: A package for an electronic component, the package comprising a front end, a back end, and an active membrane layer sandwiched between front and back electrodes of conducting material; wherein front electrode has a surface that extends beyond an adjacent surface of the active membrane layer, the active membrane mechanically supported by the front end and covered by a back end comprising at least one back cavity having organic walls and lid of organic material, with filled through vias traversing the organic walls and lid for coupling to the electrodes by an internal routing layer; the vias being coupleable by external solderable bumps to a circuit board for coupling the package in a flip chip configuration.

Abstract: A package for an electronic component wherein the package comprises a front end, a back end, and an active membrane layer sandwiched between front and back electrodes of conducting material; the active membrane being mechanically supported by the front end and covered by a back end comprising at least one back cavity having organic walls and lid, with filled through vias traversing the organic lid and walls for coupling to the electrodes by an internal routing layer; the vias being coupleable by external solderable bumps to a circuit board for coupling the package in a ‘flip chip’ configuration.

Abstract: A package for an electronic component wherein the package comprises a front end, a back end, and an active membrane layer sandwiched between front and back electrodes of conducting material; the active membrane being mechanically supported by the front end and covered by a back end comprising at least one back cavity having organic walls and lid, with filled through vias traversing the organic lid and walls for coupling to the electrodes by an internal routing layer; the vias being coupleable by external solderable bumps to a circuit board for coupling the package in a ‘flip chip’ configuration.

Abstract: A packaged electronic component comprising: an electrical element packaged within a package comprising a front part of a package comprising an inner section with a cavity therein opposite the resonator defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads that are coupleable in a ‘flip chip’ configuration to a circuit board.

Abstract: A method for fabricating an array of front ends for an array of packaged electronic components that each comprise: an electrical element packaged within a package comprising a front part of a package comprising an inner section with a cavity therein opposite the resonator defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads that are coupleable in a ‘flip chip’ configuration to a circuit board; the method comprising the stages of: i. Obtaining a carrier substrate having an active membrane layer attached thereto by its rear surface, with a front electrode on the front surface of the active membrane layer; ii.

Abstract: A method of fabricating packaged electronic components with improved yield and at lower unit cost; the method comprising the steps of obtaining an active membrane layer on a carrier substrate, depositing a front electrode onto a front of the active membrane layer, obtaining an inner front section including at least a silicon handle or wafer, attaching an inner front end section to an outer surface of the front electrode, detaching the carrier substrate from a back surface of an active membrane on the opposite surface from the front surface on which the front electrode is deposited, patterning the active membrane layer into an array of at least one island of membrane, selectively removing the front electrode and bonding layer, selectively applying an inner passivation layer, and selectively depositing a back electrode layer on the thus exposed back surface of the active membrane.

Abstract: An LED-assisted magnifying device having a generally circularly-shaped array of LEDs adapted to provide a uniform pattern of visible illumination below a magnifying lens. An ultraviolet LED is provided as an alternate, optional light source to the generally circularly-shaped array of LEDs. A darkfield illuminator may be advantageously employed with the LED-assisted magnifying device when gemstones are being inspected.

Abstract: An LED-assisted magnifying device having a generally circularly-shaped array of LEDs adapted to provide a uniform pattern of visible illumination below a magnifying lens. An ultraviolet LED is provided as an alternate, optional light source to the generally circularly-shaped array of LEDs. A darkfield illuminator may be advantageously employed with the LED-assisted magnifying device when gemstones are being inspected.