Patents by Inventor Duane Cook
Duane Cook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7203390Abstract: An optical packaging arrangement combines a planar lightwave circuit (PLC) having an array of waveguides thereon, an array of photodetectors on a substrate to receive light beams coupled out of the PLC by the output ports, and a collimating faceplate, having a plurality of glass cores, extending between the PLC and the photodetector array for coupling the output light beams to respective photodetectors. The faceplate forms a cover for a hermetic cavity encompassing the photodetectors. The PLC is disposed either co-planarly with the faceplate or transversely to it. Light from the PLC is tapped via a plurality of taps formed on the PLC for coupling to the photodetectors.Type: GrantFiled: August 10, 2005Date of Patent: April 10, 2007Assignee: JDS Uniphase CorporationInventors: Douglas E. Crafts, James F. Farrell, Mark B. Farrelly, Duane Cook, Satyanarayana Rao Peddada
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Patent number: 7141448Abstract: An integrated circuit package which may include the dispense of a second encapsulant material (or fillet) different from the first underfill material on an integrated circuit package which may include an integrated circuit that is mounted to a substrate. The package may further have a first underfill material and a second underfill material that are attached to the integrated circuit and the substrate. The second encapsulant material may be tailored to inhibit cracking of the epoxy itself that propagates into the substrate during thermo-mechanical loading.Type: GrantFiled: June 5, 2001Date of Patent: November 28, 2006Assignee: Intel CorporationInventors: Suresh Ramalingam, Venkatesan Murali, Duane Cook
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Publication number: 20060034561Abstract: An optical packaging arrangement combines a planar lightwave circuit (PLC) having an array of waveguides thereon, an array of photodetectors on a substrate to receive light beams coupled out of the PLC by the output ports, and a collimating faceplate, having a plurality of glass cores, extending between the PLC and the photodetector array for coupling the output light beams to respective photodetectors. The faceplate forms a cover for a hermetic cavity encompassing the photodetectors. The PLC is disposed either co-planarly with the faceplate or transversely to it. Light from the PLC is tapped via a plurality of taps formed on the PLC for coupling to the photodetectors.Type: ApplicationFiled: August 10, 2005Publication date: February 16, 2006Inventors: Douglas Crafts, James Farrell, Mark Farrelly, Duane Cook, Satyanarayana Peddada
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Publication number: 20060001310Abstract: A lug bolt adapted for use on an automobile having at least a double lead to decrease the number turns a lug nut requires to screw the lug nut onto the lug bolt. The lug bolt may comprise a triple or quadruple lead, or even more leads. A racing automobile may be provided having the lug bolt for the mounting of a wheel thereon using a correspondingly-leaded lug nut. The racing automobile may be a NASCAR automobile, in one embodiment.Type: ApplicationFiled: June 30, 2005Publication date: January 5, 2006Inventors: Douglas Crafts, Steve Swain, Duane Cook, Gilbert Rothweiler
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Patent number: 6945708Abstract: An optical packaging arrangement combines a planar lightwave circuit (PLC) having an array of waveguides thereon, an array of photodetectors on a substrate to receive light beams coupled out of the PLC by the output ports, and a collimating faceplate, having a plurality of glass cores, extending between the PLC and the photodetector array for coupling the output light beams to respective photodetectors. The faceplate forms a cover for a hermetic cavity encompassing the photodetectors. The PLC is disposed either co-planarly with the faceplate or transversely to it. Light from the PLC is tapped via a plurality of taps formed on the PLC for coupling to the photodetectors.Type: GrantFiled: February 18, 2003Date of Patent: September 20, 2005Assignee: JDS Uniphase CorporationInventors: Douglas E. Crafts, James F. Farrell, Mark B. Farrelly, Duane Cook, Satyanarayana Rao Peddada
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Patent number: 6907147Abstract: A capillary has an opening of a dimension for accommodating an insertion of a first and second optical fiber, a clamp to provide a clamping force to the capillary to removably couple the capillary to the clamp, and a capillary rotator removably coupled to the capillary to apply a rotational force to the capillary which is greater than the capillary force, to rotate the capillary to a selected position. An optical fiber rotator can be disposed adjacent to the first optical fiber to rotate the first optical fiber such that the first optical fiber has a selected orientation with respect to the second optical fiber.Type: GrantFiled: March 30, 2001Date of Patent: June 14, 2005Assignee: Intel CorporationInventors: Douglas E. Crafts, Duane Cook, Arne Schonert, Steve Swain
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Publication number: 20050100261Abstract: A capillary has an opening of a dimension for accommodating an insertion of a first and a second optical fiber, a clamp to provide a clamping force to the capillary to removably couple the capillary to the clamp, and a capillary rotator removably coupled to the capillary to apply a rotational force to the capillary which is greater than the capillary force, to rotate the capillary to a selected position. An optical fiber rotator can be disposed adjacent to the first optical fiber to rotate the first optical fiber such that the first optical fiber has a selected orientation with respect to the second optical fiber.Type: ApplicationFiled: March 30, 2001Publication date: May 12, 2005Inventors: Douglas Crafts, Duane Cook, Arne Schonert, Steve Swain
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Publication number: 20040161186Abstract: An optical packaging arrangement combines a planar lightwave circuit (PLC) having an array of waveguides thereon, an array of photodetectors on a substrate to receive light beams coupled out of the PLC by the output ports, and a collimating faceplate, having a plurality of glass cores, extending between the PLC and the photodetector array for coupling the output light beams to respective photodetectors. The faceplate forms a cover for a hermetic cavity encompassing the photodetectors. The PLC is disposed either co-planarly with the faceplate or transversely to it. Light from the PLC is tapped via a plurality of taps formed on the PLC for coupling to the photodetectors.Type: ApplicationFiled: February 18, 2003Publication date: August 19, 2004Applicant: JDS Uniphase Corporation, State of Incorporation: DelawareInventors: Douglas E. Crafts, James F. Farrell, Mark B. Farrelly, Duane Cook, Satyanarayana Rao Peddada
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Patent number: 6606425Abstract: An optical component package, in which a transfer molded layer of material (e.g., syntactic foam in one embodiment) is formed at least partially around, or entirely around, the optical component to provide structural and thermal insulation around the component. The optical component may be a planar lightwave circuit (PLC), with a protective passivation layer formed between the PLC and the layer of syntactic foam, to de-couple stresses and thermal transfer between the PLC and the layer of syntactic foam. Strengthening caps, fiber assemblies, and a heater may be provided with the PLC assembly, around which the layer of syntactic foam can also be formed. The protective passivation layer can also be formed between these structures and the syntactic foam; in one embodiment between at least two strengthening caps formed on opposing edges of the PLC. The disclosed package provides numerous structural, thermal and size benefits.Type: GrantFiled: March 18, 2002Date of Patent: August 12, 2003Assignee: JDS Uniphase CorporationInventors: Douglas E. Crafts, Kenzo Ishida, David J. Chapman, Duane Cook, James F. Farrell, Suresh Ramalingam, Steven M. Swain
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Patent number: 6528345Abstract: A high throughput process line and method for underfilling an integrated circuit that is mounted to a substrate. The process line includes a first dispensing station that dispenses a first underfill material onto the substrate and an oven which moves the substrate while the underfill material flows between the integrated circuit and the substrate. The process line removes flow time (wicking time) as the bottleneck for achieving high throughput.Type: GrantFiled: March 3, 1999Date of Patent: March 4, 2003Assignee: Intel CorporationInventors: Duane Cook, Suresh Ramalingam
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Patent number: 6351693Abstract: A computerized system is provided that shows a visual representation of thermostat programming information and provides context-sensitive help. The system automatically detects communicating thermostats on a network upon starting, and gives a visual representation of the stages of thermostat programming. The system further provides a visual representation of programming details of a user-selected stage while providing the representation of all stages, and allows selection of stages for display or modification of programming details in any order. The system also provides context-sensitive help for each of the stages and for each of the programming details of each stage when selected, in the form of instruction text and pop-up clarifying text.Type: GrantFiled: January 22, 1999Date of Patent: February 26, 2002Assignee: Honeywell International Inc.Inventors: Vijaykumar Subramonie Monie, Richard Daniel Hamann, Stephen Duane Cook, Premraj K. Mannikkath, Rajesh K. Vasudevan
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Publication number: 20020017728Abstract: An integrated circuit package which may include the dispense of a second encapsulant material (or fillet) different from the first underfill material on an integrated circuit package which may include an integrated circuit that is mounted to a substrate. The package may further have a first underfill material and a second underfill material that are attached to the integrated circuit and the substrate. The second encapsulant material may be tailored to inhibit cracking of the epoxy itself that propagates into the substrate during thermo-mechanical loading.Type: ApplicationFiled: June 5, 2001Publication date: February 14, 2002Inventors: Suresh Ramalingam, Venkatesan Murali, Duane Cook
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Publication number: 20020014688Abstract: An integrated circuit package which may include the dispense of a second encapsulant material (or fillet) different from the first underfill material on an integrated circuit package which may include an integrated circuit that is mounted to a substrate. The package may further have a first underfill material and a second underfill material that are attached to the integrated circuit and the substrate. The second encapsulant material may be tailored to inhibit cracking of the epoxy itself that propagates into the substrate during thermo-mechanical loading.Type: ApplicationFiled: March 3, 1999Publication date: February 7, 2002Inventors: SURESH RAMALINGAM, VENKATESAN MURALI, DUANE COOK
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Patent number: 6331446Abstract: A partial gel step in the underfilling of an integrated circuit that is mounted to a substrate. The process involves dispensing a first underfill material and then heating the underfill material to a partial gel state. The partial gel step may reduce void formation and improve adhesion performance during moisture loading.Type: GrantFiled: March 3, 1999Date of Patent: December 18, 2001Assignee: Intel CorporationInventors: Duane Cook, Venkatesan Murali, Suresh Ramalingam, Nagesh Vodrahalli