Patents by Inventor Duane E. Galbi

Duane E. Galbi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230333921
    Abstract: Examples described herein relate to a host interface and circuitry. In some examples, the circuitry, when coupled to a physical device, is to: perform operations of a hypervisor. In some examples, the host interface is configured to route first communications to the circuitry instead of the physical device and route second communications to the physical device. In some examples, the physical device is accessible as a virtual device via the host interface.
    Type: Application
    Filed: February 21, 2023
    Publication date: October 19, 2023
    Inventors: Noam ELATI, Piotr UMINSKI, Boris KLEIMAN, Lloyd DCRUZ, Bradley A. BURRES, Salma Mirza JOHNSON, Thomas E. WILLIS, Duane E. GALBI
  • Patent number: 11699471
    Abstract: An apparatus is described. The apparatus includes logic circuitry to multiplex on a data bus a first data burst, a second data burst, a third data burst and a fourth data burst having different respective base target addresses that respectively target a first memory rank, a second memory rank, a third memory rank and a fourth memory rank. A first data transfer for the first data burst occurs on a first edge of a first pulse of a data strobe signal for the data bus and a second data transfer for the second data burst occurs on a second edge of the first pulse of the data strobe signal. A third data transfer for the third data burst occurs on a first edge of a second pulse of the data strobe signal for the data bus and a fourth data transfer for the fourth data burst occurs on a second edge of the second pulse. The second pulse immediately follows the first pulse on the data strobe signal.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Duane E. Galbi, Bill Nale
  • Publication number: 20230215493
    Abstract: Methods and apparatus for Cross DRAM DIMM sub-channel pairing. Memory channels on a memory controller or System on a Chip (SoC) are segmented into two subchannels, each including Command and Address (C/A) signals, DQ (data) lines. Under different solutions the two subchannels may share a command-bus clock or use separate command-bus clocks. Some approaches use subchannels from different memory channels to provide the C/A and DQ lines for two subchannels to a given DIMM. One solution implements an additional command-bus clock on the DIMM connector repurposing existing MCR pins to provide command-bus clock signals to a Registered Clock Driver (RCD) to allow the subchannels to be fully independent. Another solution is the pair every other DRAM controller to the same command-bus clock. Other solutions employ Skip-1, Skip-2, and Skip-3 configurations under which the clocks for the DDR-IO circuitry are not logically co-located with the subchannel IO circuitry.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Inventors: Duane E. GALBI, Matthew J. ADILETTA, Mohammad M. RASHID, Todd HINCK, Vijaya K. BODDU
  • Publication number: 20230185760
    Abstract: Methods, apparatus, and software and for hardware microservices accelerated in other processing units (XPUs). The apparatus may be a platform including a System on Chip (SOC) and an XPU, such as a Field Programmable Gate Array (FPGA). The FPGA is configured to implement one or more Hardware (HW) accelerator functions associated with HW microservices. Execution of microservices is split between a software front-end that executes on the SOC and a hardware backend comprising the HW accelerator functions. The software front-end offloads a portion of a microservice and/or associated workload to the HW microservice backend implemented by the accelerator functions. An XPU or FPGA proxy is used to provide the microservice front-ends with shared access to HW accelerator functions, and schedules/multiplexes access to the HW accelerator functions using, e.g., telemetry data generated by the microservice front-ends and/or the HW accelerator functions.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Inventors: Susanne M. BALLE, Duane E. GALBI, Andrzej KURIATA, Sundar NADATHUR, Nagabhushan CHITLUR, Francesc GUIM BERNAT, Alexander BACHMUTSKY
  • Publication number: 20220321491
    Abstract: Examples described herein relate to a network interface device that includes circuitry to process data and circuitry to split a received flow of a mixture of control and data content and provide the control content to a control plane processor and provide the data content for access to the circuitry to process data, wherein the mixture of control and data content are received as part of a Remote Procedure Call. In some examples, provide the control content to a control plane processor, the circuitry is to remove data content from a received packet and include an indicator of a location of removed data content in the received packet.
    Type: Application
    Filed: June 20, 2022
    Publication date: October 6, 2022
    Inventors: Susanne M. BALLE, Shihwei CHIEN, Duane E. GALBI, Nagabhushan CHITLUR
  • Publication number: 20220321434
    Abstract: Reliability and performance of a data center is increased by processing telemetry data in a network device in the data center. A Telemetry Correlation Engine (TCE) in the network device correlates host level telemetry received from a compute node with low-level network device telemetry collected in the network device to identify performance bottlenecks for microservices based applications. The Telemetry Correlation Engine processes and analyzes the telemetry data from the compute node and network statistics available in the network device.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 6, 2022
    Inventors: Andrzej KURIATA, Francesc GUIM BERNAT, Karthik KUMAR, Susanne M. BALLE, Alexander BACHMUTSKY, Duane E. GALBI, Nagabhushan CHITLUR, Sundar NADATHUR
  • Publication number: 20220206864
    Abstract: Examples described herein relate to causing execution of a workload on a device based on characteristics of the device and based on metadata associated with the device identifying execution requirements and software and hardware compatibilities between the device and a platform environment. In some examples, an accelerator device is selected to execute a workload based on characteristics of the accelerator device and based on software and hardware compatibilities between the device and a platform environment of the accelerator device.
    Type: Application
    Filed: March 14, 2022
    Publication date: June 30, 2022
    Inventors: Sundar NADATHUR, Susanne M. BALLE, Andrzej KURIATA, Duane E. GALBI, Nagabhushan CHITLUR, Francesc GUIM BERNAT, Alexander BACHMUTSKY
  • Publication number: 20220113911
    Abstract: Methods, apparatus, and software for remote storage of hardware microservices hosted on other processing units (XPUs) and SOC-XPU Platforms. The apparatus may be a platform including a System on Chip (SOC) and an XPU, such as a Field Programmable Gate Array (FPGA). Software, via execution on the SOC, enables the platform to pre-provision storage space on a remote storage node and assign the storage space to the platform, wherein the pre-provisioned storage space includes one or more container images to be implemented as one or more hardware (HW) microservice front-ends. The XPU/FPGA is configured to implement one or more accelerator functions used to accelerate HW microservice backend operations that are offloaded from the one or more HW microservice front-ends. The platform is also configured to pre-provision a remote storage volume containing worker node components and access and persistently store worker node components.
    Type: Application
    Filed: December 21, 2021
    Publication date: April 14, 2022
    Inventors: Andrzej KURIATA, Susanne M. BALLE, Duane E. GALBI, Sundar NADATHUR, Nagabhushan CHITLUR, Francesc GUIM BERNAT, Alexander BACHMUTSKY
  • Publication number: 20220012126
    Abstract: A translation cache and configurable error checking and correction (“ECC”) memory reduces ECC memory overhead. The translation cache supports a configurable ECC memory capable of storing a portion of a cache line, along with any ECC data, in corresponding parts of memory devices to reduce the ECC memory overhead in a memory subsystem. The corresponding parts include any same one of an upper, lower, left or right part of memory devices in a memory module, including dynamic random access memory (“DRAM”) devices in a dual inline memory module (“DIMM”).
    Type: Application
    Filed: September 23, 2021
    Publication date: January 13, 2022
    Inventors: Duane E. GALBI, Wim HEIRMAN, Dimitrios ZIAKAS
  • Publication number: 20220012173
    Abstract: A memory system has a configurable mapping of address space of a memory array to address of a memory access command. In response to a memory access command, a memory device can apply a traditional mapping of the command address to the address space, or can apply an address remapping to remap the command address to different address space.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Duane E. GALBI, Kuljit S. BAINS
  • Publication number: 20220012195
    Abstract: A memory system has a configurable mapping of address space of a memory array to address of a memory access command. A controller provides command and enable information specific to a memory device. The command and enable information can cause the memory device to apply a traditional mapping of the command address to the address space, or can cause the memory device to apply an address remapping to remap the command address to different address space.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Duane E. GALBI, Kuljit S. BAINS
  • Publication number: 20210209035
    Abstract: Examples described herein relate to an apparatus that includes at least two processing units and a memory hub coupled to the at least two processing units. In some examples, the memory hub includes a home agent. In some examples, the memory hub is to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub. In some examples, the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub. In some examples, the first processing unit comprises a second home agent and wherein the second home agent is to perform the at least some but not all home agent operations before the offload of at least some but not all home agent operations to the home agent of the memory hub.
    Type: Application
    Filed: March 25, 2021
    Publication date: July 8, 2021
    Inventors: Duane E. GALBI, Matthew J. ADILETTA, Hugh WILKINSON, Patrick CONNOR
  • Publication number: 20210191811
    Abstract: An apparatus is described. The apparatus includes a memory controller having logic circuitry to write a unit of write data into a plurality of memory chips according to a striping pattern that includes multiple protected sub words, each protected sub word including a smaller portion of the unit of write data and error correction coding (ECC) information calculated from the smaller portion of the unit of write data.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 24, 2021
    Inventors: Duane E. GALBI, Matthew J. ADILETTA
  • Publication number: 20210005234
    Abstract: An apparatus is described. The apparatus includes logic circuitry to multiplex on a data bus a first data burst, a second data burst, a third data burst and a fourth data burst having different respective base target addresses that respectively target a first memory rank, a second memory rank, a third memory rank and a fourth memory rank. A first data transfer for the first data burst occurs on a first edge of a first pulse of a data strobe signal for the data bus and a second data transfer for the second data burst occurs on a second edge of the first pulse of the data strobe signal. A third data transfer for the third data burst occurs on a first edge of a second pulse of the data strobe signal for the data bus and a fourth data transfer for the fourth data burst occurs on a second edge of the second pulse. The second pulse immediately follows the first pulse on the data strobe signal.
    Type: Application
    Filed: September 23, 2020
    Publication date: January 7, 2021
    Inventors: Duane E. GALBI, Bill NALE
  • Publication number: 20200125495
    Abstract: An apparatus is described. The apparatus includes a semiconductor chip package. The semiconductor chip package includes an SOC. The SOC has a memory controller. The semiconductor chip package includes an interface to an external memory. The semiconductor chip package includes a memory side cache. The memory side cache is composed of eDRAM and is coupled between the memory controller and the interface to the external memory. The eDRAM is to cache more frequently used items of the external memory. The semiconductor chip package has an out-of-order interface between the memory controller and the memory side cache.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: Duane E. GALBI, Bradley A. BURRES, Matthew J. ADILETTA, Hugh WILKINSON, Aaron GORIUS
  • Patent number: 8331133
    Abstract: Approaches to organizing/constructing a register file base cell in a way that reduces the number of signals which need to be routed to and through the bit base cell are disclosed. Base cells so constructed allow industry standard static timing approaches and tools to verify the timing of a register file comprised of such base cells as a whole and allow industry standard place-and-route (APR) tools to be used to implement the connections between the base cells and the other register file logic not directly included in the base cell.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: December 11, 2012
    Assignee: Intel Corporation
    Inventor: Duane E. Galbi
  • Publication number: 20100332712
    Abstract: Approaches to organizing/constructing a register file base cell in a way that reduces the number of signals which need to be routed to and through the bit base cell are disclosed. Base cells so constructed allow industry standard static timing approaches and tools to verify the timing of a register file comprised of such base cells as a whole and allow industry standard place-and-route (APR) tools to be used to implement the connections between the base cells and the other register file logic not directly included in the base cell.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Inventor: Duane E. Galbi
  • Publication number: 20100027781
    Abstract: A method and apparatus for increasing performance of Data Encryption Standard (DES) and Triple DES (3DES) cipher operation is provided. A critical path through a plurality of rounds in a multi-round cycle to perform a cipher operation is reduced by reducing the number of exclusive OR (XOR) operations in the critical path. An R state element is expanded to 48-bits and each round stage uses the 48-bit expanded R state element which results in a reduction of the number of XOR operations to one per round in the cipher operation plus one additional XOR operation per cipher operation. In addition logic organization is symmetric which further increases the overall performance of DES and 3DES.
    Type: Application
    Filed: December 20, 2007
    Publication date: February 4, 2010
    Inventors: Duane E. Galbi, David G. Lewis, Kirk S. Yap
  • Patent number: 7533286
    Abstract: In general, in one aspect, the disclosure describes an apparatus for engineering di/dt. The apparatus includes a plurality of functional blocks to perform different functions. The apparatus also includes a clock source to provide a clock signal to said plurality of functional blocks. At least one gating device is used to regulate application of the clock to the plurality of functional blocks. A controller is included to control the at least one gating device and turning-on of the clock signal.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Praveen Mosur, Duane E. Galbi, Benjamin J. Cahill
  • Patent number: 7447948
    Abstract: Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: November 4, 2008
    Assignee: Intel Corporation
    Inventors: Duane E. Galbi, Ranjit Loboprabhu, Jose Niell