Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures of transistor gate oxide. A methodology is provided that is a practical approach to full-chip crosstalk noise verification and gate oxide integrity analysis. A grouping based method is described for identification of potential victims and associated aggressors, using either timing information or functional information. Potential victim signal lines are selected and pruned based on total coupling capacitance to various signal groups. Selected signal lines are then fully simulated to determine gate oxide field strengths on transistors connected to the selected signal lines.

Abstract: A method for designing and fabricating an integrated circuit is disclosed. Signal line interconnect widths are determined by performing an electromigration analysis on a trial layout of the integrated circuit. A representative circuit for an integrated circuit is designed and a trial layout is created that includes a plurality of nets. A preprocessor 505 eliminates nets that do not need further validation. An extraction process 510 generates an RC network representation of each remaining net that is to be validated to form a distributed load simulation model. Distributed capacitance and resistance of signal lines is included with load capacitance of receivers to provide an accurate profile of current flow. A profile of current flowing in the signal line of each net is determined by simulating the operation of each net using simulator 517. Peak current, RMS current and average current is determined.