Abstract: A multimedia processor contains a general purpose RISC and video processors which operate in parallel to execute software for combined video and audio bit stream coding and decoding. The RISC processor controls operation of the multimedia processor and performs bit stream parsing and coding, audio compression and decompression, and general processing for embedded applications. The video processor performs video encoding and decoding functions such as scaling, filtering, decimation, and DCT transforms. The RISC processor and the video processor each have separate data buses which are interconnected through a portal circuit and a Huffman codec. Each data bus has a DMA controller which transfers data to and from a memory interface to an external memory. DMA channels serve I/O interface resources coupled to the data buses and can form buffers in the external memory. This reduces the need for on-chip FIFO buffers and separate buffers between the multimedia processor and attached devices.