Abstract: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load address is correct but preferably includes dependence according to the original source code. The compiler may statically schedule two or more branches in parallel with orthogonal conditions.

Abstract: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load address is correct but preferably includes dependence according to the original source code. The compiler may statically schedule two or more branches in parallel with orthogonal conditions.

Abstract: A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the “1” to the carry in of the two's complement arithmetic unit. To execute a subtraction instruction using two's complement arithmetic, the subtraction as disclosed herein is performed in accordance with the identity “A?B=not (not (A)+B),” where A is a first operand and B is a second operand that is to be subtracted from A. Accordingly, the addition of the “1” term into the carry in is eliminated, and reduces a level of complexity that would otherwise slow down and/or limit the speed at which a subtraction instruction can be performed.

Abstract: A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the “1” to the carry in of the two's complement arithmetic unit. To execute a subtraction instruction using two's complement arithmetic, the subtraction as disclosed herein is performed in accordance with the identity “A?B=not (not (A)+B),” where A is a first operand and B is a second operand that is to be subtracted from A. Accordingly, the addition of the “1” term into the carry in is eliminated, and reduces a level of complexity that would otherwise slow down and/or limit the speed at which a subtraction instruction can be performed.

Abstract: Logic circuitry (70, 80, 90) for performing fault detection in a microprocessor (5) is disclosed. The fault detection logic circuitry (70, 80, 90) may be implemented into a scheduler (50) in a floating-point unit (31). Mask register (M) bit positions (M.sub.0 through M.sub.7) store state information relative to registers (52) or other resources in the microprocessor (5) that is to be interrogated upon scheduling of an instruction. The instruction includes an encoded address communicated on register address lines (SA) that is received by the fault detection logic circuitry (70, 80, 90). Pass gates (72) are controlled by the encoded address on the register address lines (SA) to generate a fault indicator (FLT). Partitioning of the decoding of the encoded address may be utilized for optimization of the fault detection operation.

Abstract: A microprocessor (10) and system implementing the same is disclosed, in which stack-based register address calculation is performed in a single add cycle for instructions involving a PUSH operation. The microprocessor (10) includes a floating-point unit (FPU) (31) having a register stack (52.sub.ST) and a stack pointer (FSP), for executing floating-point instructions containing relative register addresses (REG) based upon the contents (TOP) of the stack pointer (FSP). The instructions may involve PUSH operations, in which an operand is added to the stack of operands in the register stack (52.sub.ST). Register addressing circuitry (125, 125') includes an adder (122; 122') for generating the sum of the contents (TOP) of the stack pointer (FSP) and the relative register address (REG) of the instruction, and an adder/decrementer (120) for generating the sum of the contents (TOP) of the stack pointer (FSP) and the relative register address (REG) of the instruction minus one, to account for the PUSH.