Patents by Inventor Duck Hoi KOO
Duck Hoi KOO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934271Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a plurality of storage regions, each including a plurality of memory cells; and a controller configured to provide a plurality of read retry sets, determine an applying order of the plurality of read retry sets based on characteristics of a read error occurred in a first storage region among the plurality of storage regions, and apply at least one of the read retry sets, based on the applying order, for a read retry operation performed on the first storage region.Type: GrantFiled: December 29, 2021Date of Patent: March 19, 2024Assignee: SK hynix Inc.Inventors: Nam Oh Hwang, Yong-Tae Kim, Soong-Sun Shin, Duck-Hoi Koo
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Patent number: 11474726Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method thereof, in which a data storage space of a memory device is divided into N namespaces, and in which each namespace is controlled so as to share a super memory block with other namespaces or to occupy the same exclusively, thereby minimizing an increase in the time taken to format each of a plurality of namespaces while efficiently storing data in a plurality of namespaces.Type: GrantFiled: August 7, 2020Date of Patent: October 18, 2022Assignee: SK hynix Inc.Inventors: Duck Hoi Koo, In Ho Jung
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Patent number: 11455120Abstract: A memory system may include: a memory device comprising a plurality of channels, a plurality of dies coupled to the respective channels, and a plurality of super blocks; and a controller suitable for controlling the memory device, wherein the controller includes: a detector suitable for searching for a first available reserved block in a first die, when a bad block has occurred in the first die which is coupled to a first channel and belongs to a first super block group, and searching for a second available reserved block in a second die which is coupled to the first channel and belongs to a second super block group when the first available reserved block is not present in the first die; and an assignor suitable for replacing the bad block with the second available reserved block when the second available reserved block is present.Type: GrantFiled: October 1, 2020Date of Patent: September 27, 2022Assignee: SK hynix Inc.Inventors: Duck-Hoi Koo, Yong-Tae Kim
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Patent number: 11327885Abstract: There are provided a controller and a memory system having the controller.Type: GrantFiled: May 20, 2020Date of Patent: May 10, 2022Assignee: SKhynix Inc.Inventors: Duck Hoi Koo, Gun Woo Yeon, Young Ho Kim, Seung Geol Baek, Suk Ho Jung
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Patent number: 11314453Abstract: A memory system includes: a memory device including: a first memory block storing first map data, which maps a first logical address to a first physical address; and a second memory block storing first user data corresponding to the first map data; and a controller configured to: receive a warning signal from a host; and back up the first map data as second map data in response to the first logical address being provided along with a write command received after the warning signal is received; update the first map data to map the first logical address to a second physical address; suspend an erase operation being performed on the first user data is invalidated due to the write command; and restore the first map data based on the second map data and validate the invalidated first user data when it is determined that the host is infected by malware.Type: GrantFiled: May 11, 2020Date of Patent: April 26, 2022Assignee: SK hynix Inc.Inventors: Jong-Pil Jung, Duck-Hoi Koo
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Publication number: 20220121520Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a plurality of storage regions, each including a plurality of memory cells; and a controller configured to provide a plurality of read retry sets, determine an applying order of the plurality of read retry sets based on characteristics of a read error occurred in a first storage region among the plurality of storage regions, and apply at least one of the read retry sets, based on the applying order, for a read retry operation performed on the first storage region.Type: ApplicationFiled: December 29, 2021Publication date: April 21, 2022Inventors: Nam Oh HWANG, Yong-Tae KIM, Soong-Sun SHIN, Duck-Hoi KOO
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Patent number: 11249917Abstract: An operating method for a data storage device includes providing a nonvolatile memory device including a plurality of pages; segmenting an address map which maps a logical address provided from a host device and a physical address of the nonvolatile memory device, by a plurality of address map segments according to a segment size that is set depending on a quality of service time allowed to process a request of the host device and an unprocessed workload; and flushing at least one of the address map segments in the nonvolatile memory device after processing the unprocessed workload.Type: GrantFiled: April 17, 2020Date of Patent: February 15, 2022Assignee: SK hynix Inc.Inventors: Min Hwan Moon, Duck Hoi Koo, Soong Sun Shin, Ji Hoon Lee
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Patent number: 11237908Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a plurality of storage regions, each including a plurality of memory cells; and a controller configured to provide a plurality of read retry sets, determine an applying order of the plurality of read retry sets based on characteristics of a read error occurred in a first storage region among the plurality of storage regions, and apply at least one of the read retry sets, based on the applying order, for a read retry operation performed on the first storage region.Type: GrantFiled: February 24, 2020Date of Patent: February 1, 2022Assignee: SK hynix Inc.Inventors: Nam Oh Hwang, Yong-Tae Kim, Soong-Sun Shin, Duck-Hoi Koo
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Patent number: 11169871Abstract: A data storage device includes a nonvolatile memory device including a plurality of memory blocks and a controller for controlling the nonvolatile memory device. A plurality of management blocks includes first and second management blocks managed by the controller. The second management block stores start data and then stores integrity data. The first management block stores a storage location of the second management block. An integrity checker checks integrity of data associated with the first and second management blocks.Type: GrantFiled: April 13, 2020Date of Patent: November 9, 2021Assignee: SK hynix Inc.Inventors: Jang Hwan Jun, Duck Hoi Koo, Soong Sun Shin, Yong Tae Kim, Yong Chul Kim, Cheon Ok Jeong
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Patent number: 11086720Abstract: A memory system may include: a memory device including a plurality of storage regions; and a controller. The controller may be coupled between a host and the memory device, and perform a read retry operation when a read error occurs in any one of the storage regions based on occurrence possibilities for a plurality of different type of defects in any one storage region where a read error occurred.Type: GrantFiled: August 6, 2019Date of Patent: August 10, 2021Assignee: SK hynix Inc.Inventors: Yong-Tae Kim, Soong-Sun Shin, Duck-Hoi Koo
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Patent number: 11061607Abstract: There are provided an electronic system and an operating method thereof. The electronic system includes: a host for queuing an external command to wait or to be output, based on a status of dies included in a storage device; a central processing unit for generating a command for controlling the storage device in response to a request received from the host or the external command; and a controller memory buffer for storing status information indicating whether the dies are in a status in which access is possible or a status in which access is impossible, wherein the central processing unit receives status information of the dies from the storage device, and stores status information matched to each of the dies in the controller memory buffer.Type: GrantFiled: August 28, 2018Date of Patent: July 13, 2021Assignee: SK hynix Inc.Inventors: Duck Hoi Koo, Yong Jin
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Publication number: 20210165736Abstract: There are provided a controller and a memory system having the controller. The controller includes: a first storage area configured to store mapping information between logical addresses of logical regions of a storage device coupled to the controller and physical addresses of memory blocks of the storage device, the logical regions being divided into logical units including a first logical unit; and a second storage area configured to store allocation information on logical addresses of logical regions allocated to the first logical unit, each of the logical regions allocated to the first logical unit having a corresponding index, wherein the second storage area is further configured to store a location table including index information on a smallest index among indices corresponding to the logical regions allocated to the first logical unit and number information on a total number of the logical regions allocated to the first logical unit.Type: ApplicationFiled: May 20, 2020Publication date: June 3, 2021Inventors: Duck Hoi Koo, Gun Woo Yeon, Young Ho Kim, Seung Geol Baek, Suk Ho Jung
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Publication number: 20210157524Abstract: A memory system includes: a memory device including: a first memory block storing first map data, which maps a first logical address to a first physical address; and a second memory block storing first user data corresponding to the first map data; and a controller configured to: receive a warning signal from a host; and back up the first map data as second map data in response to the first logical address being provided along with a write command received after the warning signal is received; update the first map data to map the first logical address to a second physical address; suspend an erase operation being performed on the first user data is invalidated due to the write command; and restore the first map data based on the second map data and validate the invalidated first user data when it is determined that the host is infected by malware.Type: ApplicationFiled: May 11, 2020Publication date: May 27, 2021Inventors: Jong-Pil JUNG, Duck-Hoi KOO
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Publication number: 20210141554Abstract: A memory system includes a plurality of nonvolatile memory apparatuses; and a controller including cache areas respectively corresponding to the plurality of nonvolatile memory apparatuses, each of the cache areas storing cache data of a corresponding nonvolatile memory apparatus, wherein the controller adjusts a size of at least one of the cache areas based on read queue depths of command queues respectively corresponding to the plurality of nonvolatile memory apparatuses.Type: ApplicationFiled: August 5, 2020Publication date: May 13, 2021Inventors: Duck Hoi KOO, Soong Sun SHIN
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Patent number: 10997039Abstract: A method for operating a data storage device which includes a nonvolatile memory device including a plurality of memory blocks, includes generating a valid page count table including the number of valid pages of each of closed blocks among the plurality of memory blocks in which data are written in all pages thereof and the number of valid pages of at least one open block among the plurality of memory blocks in which data is written in a part of pages thereof; generating a valid page scan table including a scan pointer for scanning the number of valid pages of the open block; and backing up the valid page count table and the valid page scan table in a meta block among the plurality of memory blocks.Type: GrantFiled: August 28, 2019Date of Patent: May 4, 2021Assignee: SK hynix Inc.Inventors: Duck Hoi Koo, Yong Tae Kim, Soong Sun Shin, Cheon Ok Jeong
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Patent number: 10949105Abstract: A data storage device may include: a memory device; and a controller configured to control an operation of the memory device. The controller may include a first CPU and a second CPU including a plurality of cores, wherein the first CPU compares P/E (Program/Erase) average counts for the plurality of cores of the second CPU, and performs a remapping operation of changing a core which is mapped to logical block addresses received from a host.Type: GrantFiled: October 22, 2019Date of Patent: March 16, 2021Assignee: SK hynix Inc.Inventors: Duck Hoi Koo, Seung Geol Baek, Young Ho Kim, Suk Ho Jung
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Patent number: 10942862Abstract: A memory system includes a memory device comprising a plurality of memory cells storing data, and configured to perform one or more of a write operation, read operation and erase operation on the plurality of memory cells; and a controller configured to control an operation of the memory device, wherein the controller is configured to: cache a logical block addressing (LBA) mapping table from the memory device when the memory system is powered on by driving power applied thereto; and transfer a direct memory access (DMA) setup to a host when the LBA mapping table is cached.Type: GrantFiled: April 29, 2019Date of Patent: March 9, 2021Assignee: SK hynix Inc.Inventors: Duck Hoi Koo, Soong Sun Shin, Sang Hyun Kim
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Publication number: 20210064260Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method thereof, in which a data storage space of a memory device is divided into N namespaces, and in which each namespace is controlled so as to share a super memory block with other namespaces or to occupy the same exclusively, thereby minimizing an increase in the time taken to format each of a plurality of namespaces while efficiently storing data in a plurality of namespaces.Type: ApplicationFiled: August 7, 2020Publication date: March 4, 2021Inventors: Duck Hoi KOO, In Ho JUNG
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Publication number: 20210019080Abstract: A memory system may include: a memory device comprising a plurality of channels, a plurality of dies coupled to the respective channels, and a plurality of super blocks; and a controller suitable for controlling the memory device, wherein the controller includes: a detector suitable for searching for a first available reserved block in a first die, when a bad block has occurred in the first die which is coupled to a first channel and belongs to a first super block group, and searching for a second available reserved block in a second die which is coupled to the first channel and belongs to a second super block group when the first available reserved block is not present in the first die; and an assignor suitable for replacing the bad block with the second available reserved block when the second available reserved block is present.Type: ApplicationFiled: October 1, 2020Publication date: January 21, 2021Inventors: Duck-Hoi KOO, Yong-Tae KIM
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Patent number: 10860227Abstract: Provided herein may be a memory controller, a memory system having the same, and a method of operating the same. The memory controller may include an operating environment determiner configured to determine an operating environment of a memory device based on at least one of surrounding environment-sensing data, and a central processing unit (CPU) configured to determine operating characteristics of the memory device required in the determined operating environment, select a policy depending on the determined operating characteristics, and control an operation of the memory device based on the selected policy.Type: GrantFiled: June 27, 2018Date of Patent: December 8, 2020Assignee: SK hynix Inc.Inventors: Yong Jin, Duck Hoi Koo, Jin Pyo Kim