Abstract: Package structures are provided for integrally packaging antennas with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems that operate in the millimeter-wave and terahertz frequency ranges. For example, a package structure includes an RFIC chip, and an antenna package bonded to the RFIC chip. The antenna package includes a glass substrate, at least one planar antenna element formed on a first surface of the glass substrate, a ground plane formed on a second surface of the glass substrate, opposite the first surface, and an antenna feed line formed through the glass substrate and connected to the at least one planar antenna element. The antenna package is bonded to a surface of the RFIC chip using a layer of adhesive material.

Abstract: A package structure includes a planar core structure, an antenna structure disposed on one side of the planar core structure, and an interface structure disposed on an opposite side of the planar core structure. The antenna structure and interface structure are each formed of a plurality of laminated layers, each laminated layer having a patterned conductive layer formed on an insulating layer. The antenna structure includes a planar antenna formed on one or more patterned conductive layers of the laminated layers. The interface structure includes a power plane, a ground plane, signal lines, and contact pads formed on one or more patterned conductive layers of the laminated layers of the interface structure. The package structure further includes an antenna feed line structure formed in, and routed through, the interface structure and the planar core structure, and connected to the planar antenna.

Abstract: A chip package includes a set of layers including conductive planes connected by vias. A first portion has at least one antenna, antenna ground plane, and first grounded vias. A second portion has a conductive plane parallel to the ground plane that forms an interface for connecting to at least one integrated circuit device. A third portion between the first and the second portion has a vertical transmission line that includes a signal via connecting the antenna feed line to the at least one integrated circuit and a parallel-plate mode suppression mechanism. The parallel-plate mode suppression mechanism includes a grounded reflector that forms a cage with the grounded vias around an antenna region and further includes second ground vias surrounding the signal via.

Abstract: Antenna devices, antenna systems and methods of their fabrication are disclosed. One such antenna device includes a semiconductor chip and a chip package. The semiconductor chip includes at least one antenna that is integrated into a dielectric layer of the semiconductor chip and is configured to transmit electromagnetic waves. In addition, the chip package includes at least one ground plane, where the semiconductor chip is mounted on the chip package such that the ground plane(s) is disposed at a predetermined distance from the antenna to implement a reflection of at least a portion of the electromagnetic waves.

Abstract: Systems, methods, devices and apparatuses directed to transceiver devices are disclosed. In accordance with one method, a first set of antenna positions in a first section of a set of sections of a circuit layout for the circuit package is selected. The method further includes selecting another set of antenna positions in another section of the circuit layout such that an arrangement of selected antenna positions of the other set is different from an arrangement of selected antenna positions of a previously selected set of antenna positions. The selecting another set of positions in another section is iterated until selections have been made for a total number of antennas. The selecting the other set is performed such that consecutive unselected positions in the other section do not exceed a predetermined number of positions. In addition, antenna elements are formed at the selected positions to fabricate the circuit package.

Abstract: A chip package includes a plurality of layers including conductive planes connected by vias. The layers include a first portion having an antenna formed therein and a parallel-plate mode suppression mechanism to suppress parallel-plate mode excitation of the antenna. The parallel-plate mode suppression mechanism includes a reflector offset from an antenna ground plane and first grounded vias. A second portion has an interface for connecting to an integrated circuit device wherein the first portion and the second portion are separated by the parallel-plate mode suppression mechanism.

Abstract: Package structures are provided having antenna-in-packages that are integrated with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems that operate in the millimeter wave (mm Wave) frequency range with radiation in broadside and end-fire directions.

Abstract: Systems and method for near-field millimeter wave imaging are provided, in particular, near-field millimeter wave imaging systems and methods that enable sub-wavelength resolution imaging by scanning objects with sub-wavelength probe elements and capturing and measuring phase and intensity of reflected energy to generate images.

Abstract: A radio frequency integrated circuit (RFIC) chip package is provided having an RFIC chip and an integrated antenna structure. The integrated antenna structure includes an on-chip antenna having one or more radiator elements formed as part of a back-end-of-line structure of the RFIC chip. The antenna structure further includes a superstrate structure disposed on the back-end-of-line structure of the RFIC chip. The superstrate structure includes at least one substrate layer and a focusing metal element. The focusing metal element has a structure that is complementary to the on-chip radiator elements and which is configured to focus electromagnetic radiation to and from the planar antenna structure. The superstrate structure improves the performance (e.g., antenna gain and bandwidth) of the on-chip antennas for millimeter-wave applications.

Abstract: Array packages and methods for forming large-scale antenna arrays. One method includes aligning two or more array packages. The two or more array packages each include one or more bottom dielectric layers, an array of antennas arranged in a plane above the one or more bottom dielectric layers, a ground plane layer above the one or more bottom dielectric layers, and a conductive surface on at least a part of an outside surface of the array package and orthogonal to the plane of the array of antennas. The conductive surface is electrically connected to the ground plane layer.

Abstract: A radio frequency integrated circuit (RFIC) chip package is provided having an RFIC chip and an integrated antenna structure. The integrated antenna structure includes an on-chip antenna having one or more radiator elements formed as part of a back-end-of-line structure of the RFIC chip. The antenna structure further includes a superstrate structure disposed on the back-end-of-line structure of the RFIC chip. The superstrate structure includes at least one substrate layer and a focusing metal element. The focusing metal element has a structure that is complementary to the on-chip radiator elements and which is configured to focus electromagnetic radiation to and from the planar antenna structure. The superstrate structure improves the performance (e.g., antenna gain and bandwidth) of the on-chip antennas for millimeter-wave applications.

Abstract: Antenna devices, antenna systems and methods of their fabrication are disclosed. One such antenna device includes a semiconductor chip and a chip package. The semiconductor chip includes at least one antenna that is integrated into a dielectric layer of the semiconductor chip and is configured to transmit electromagnetic waves. In addition, the chip package includes at least one ground plane, where the semiconductor chip is mounted on the chip package such that the ground plane(s) is disposed at a predetermined distance from the antenna to implement a reflection of at least a portion of the electromagnetic waves.

Abstract: Wafer-scale packaging structures and methods are provided for integrally packaging antenna structures with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems for millimeter wave (mmWave) and Terahertz (THz) applications. For example, a chip package includes an RFIC chip, an antenna structure and an interface layer. The RFIC chip includes a semiconductor substrate having an active surface and an inactive surface, and a BEOL (back end of line) structure formed on the active surface of the semiconductor substrate. The antenna structure includes an antenna substrate and a planar antenna radiator formed on a surface of the antenna substrate, wherein the antenna substrate is formed of a low loss semiconductor material. The interface layer connects the antenna structure to the BEOL structure of the RFIC chip.

Abstract: Apparatus and methods are provided for integrally packaging semiconductor IC (integrated circuit) chips with antennas having one or more radiating elements and tuning elements that are formed from package lead wires that are appropriated shaped and arranged to form antenna structures for millimeter wave applications.

Abstract: Apparatus and methods for packaging IC chips and laminated antenna structures with laminated waveguide structures that are integrally constructed as part of an antenna package to form compact integrated radio/wireless communications systems for millimeter wave applications.

Abstract: A circuit device includes a multilayer circuit carrier, a first signal transmission line, a second signal transmission line, a signal line transition element, a first impedance transformer, and a second impedance transformer. The multilayer circuit carrier includes a first layer and a second layer. The first signal transmission line is on the surface of the first layer. The second signal transmission line is on the surface of the second layer. The signal line transition element passes through the first layer and the second layer, and has a first signal terminal and a second signal terminal. The first impedance transformer is on the surface of the first layer and electrically connected between the first signal transmission line and the first signal terminal. The second impedance transformer is on the surface of the second layer and electrically connected between the second signal transmission line and the second signal terminal.

Abstract: Wafer-scale packaging structures and methods are provided for integrally packaging antenna structures with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems for millimeter wave (mmWave) and Terahertz (THz) applications. For example, a chip package includes an RFIC chip, an antenna structure and an interface layer. The RFIC chip includes a semiconductor substrate having an active surface and an inactive surface, and a BEOL (back end of line) structure formed on the active surface of the semiconductor substrate. The antenna structure includes an antenna substrate and a planar antenna radiator formed on a surface of the antenna substrate, wherein the antenna substrate is formed of a low loss semiconductor material. The interface layer connects the antenna structure to the BEOL structure of the RFIC chip.

Abstract: An apparatus, imager elements, and a method for detecting a radio frequency image using phased array techniques. An example apparatus includes an array of radio frequency antennas fabricated on one or more packaged integrated circuits. The apparatus also includes a controller configured to selectively phase shift radio frequency signals from the antennas such that the at least a portion of the radio frequency image is focused.

Abstract: A frequency modulation continuous wave (FMCW) system includes a first memory receiving a clock signal and storing voltage digital values of I FMCW signals, a second memory receiving the clock signal and storing the voltage digital values of the Q FMCW signals, a first digital-to-analog converter (DAC) connected to the first memory and receiving the clock signal for converting the voltage digital values of the I FMCW signal to a first analog voltage, a second digital-to-analog converter (DAC) connected to the second memory and receiving the clock signal for converting the voltage digital values of the Q FMCW signal to a second analog voltage, an I low-pass filter connected to the first DAC smoothing the I FMCW signal and a Q low-pass filter connected to the second DAC smoothing the Q FMCW signal.

Abstract: Techniques provide improved thermal interface material application in an assembly associated with an integrated circuit package. For example, an apparatus comprises an integrated circuit module, a printed circuit board, and a heat transfer device. The integrated circuit module is mounted on a first surface of the printed circuit board. The printed circuit board has at least one thermal interface material application via formed therein in alignment with the integrated circuit module. The heat transfer device is mounted on a second surface of the printed circuit board and is thermally coupled to the integrated circuit module. The second surface of the printed circuit board is opposite to the first surface of the printed circuit board.