Abstract: An image sensor includes a substrate including a first surface and a second surface opposite to the first surface; a plurality of pixel sensors disposed in the substrate, a sensor isolation feature disposed in the substrate defining an active region, and a dielectric layer between the sensor isolation feature and the substrate, wherein the sensor isolation feature comprises a conductive material.

Abstract: A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a first wafer including a plurality of electronic integrated circuits (EICs), forming a second wafer including a plurality of photonic integrated circuits (PICs), bonding the first wafer to the second wafer to form a first stacked wafer. The bonding of the first wafer to the second wafer includes vertically aligning each of the plurality of the EICs with one of the plurality of the PICs.

Abstract: A method for forming a semiconductor image sensor includes following operation. A first substrate including a first bottom side and a first top side is provided. A first interconnect structure is disposed under the first bottom side of the first substrate. An insulating structure is formed over the first top side of the first substrate. A conductor penetrating the insulating structure and the first substrate is formed and a first bonding pad is formed in the insulating structure. A second substrate including a second bottom side and a second top side is provided with the second bottom side facing the first top side of the first substrate. A second interconnect structure is disposed under the second bottom side of the second substrate, and a second bonding pad is coupled to the second interconnect structure. The first bonding pad is bonded to the second bonding pad to form a first bonded structure.

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a boundary deep trench isolation (BDTI) structure disposed at boundary regions of a pixel region surrounding a photodiode. The BDTI structure has a ring shape from a top view and two columns surrounding the photodiode with the first depth from a cross-sectional view. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel region overlying the photodiode, the MDTI structure extending from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure has three columns with the second depth between the two columns of the BDTI structure from the cross-sectional view. The MDTI structure is a continuous integral unit having a ring shape.

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a gate stack over a front surface of a substrate. A mask layer is formed over at least a portion of the gate stack and a portion of the front surface. A plurality of dopants are implanted into one or more regions of the substrate that are not covered by the mask layer to form one or more doped isolation features in the substrate. The one or more doped isolation features are formed to have a convex portion at least partially under the gate stack.

Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a bond pad structure extends to a columnar structure with a high via density. For example, an interconnect structure is on a frontside of a substrate and comprises a first bond wire, a second bond wire, and bond vias forming the columnar structure. The bond vias extend from the first bond wire to the second bond wire. The bond pad structure is inset into a backside of the substrate, opposite the frontside, and extends to the first bond wire. A projection of the first or second bond wire onto a plane parallel to a top surface of the substrate has a first area, and a projection of the bond vias onto the plane has a second area that is 10% or more of the first area, such that via density is high.

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure arranged on a first surface of a substrate. A doped isolation region is arranged within the substrate along opposing sides of the gate structure. The substrate includes a first region between sides of the doped isolation region and a second region having a different doping characteristic than the first region. The second region contacts a bottom of the first region and a bottom of the doped isolation region.

Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.

Abstract: Some embodiments relate to a method. In the method, semiconductor devices are formed on a frontside of a semiconductor substrate. A trench is formed in a backside of the semiconductor substrate. Conductive and insulating layers are alternatingly formed in the trench on the backside of the semiconductor substrate to establish a backside capacitor. A backside interconnect structure is formed on the backside of the semiconductor substrate to couple to capacitor electrodes of the backside capacitor.

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a plurality of pixel regions disposed within a substrate and respectively comprising a photodiode configured to receive radiation that enters the substrate from a back-side. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions surrounding the photodiode. The BDTI structure extends from the back-side of the substrate to a first depth within the substrate. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel regions overlying the photodiode. The MDTI structure extends from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure is a continuous integral unit having a ring shape.

Abstract: A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.

Abstract: The present disclosure relates to an image sensor having an image sensing element surrounded by a BDTI structure, and an associated method of formation. In some embodiments, a first image sensing element and a second image sensing element are arranged next to one another within an image sensing die. A pixel dielectric stack is disposed along a back of the image sensing die overlying the image sensing elements. The pixel dielectric stack includes a first high-k dielectric layer and a second high-k dielectric layer. The BDTI structure is disposed between the first image sensing element and the second image sensing element and extends from the back of the image sensor die to a position within the image sensor die. The BDTI structure includes a trench filling layer surrounded by an isolation dielectric stack. The pixel dielectric stack has a composition different from that of the isolation dielectric stack.

Abstract: A metal grid within a trench isolation structure on the back side of an image sensor is coupled to a contact pad so that a voltage on the metal grid is continuously variable with a voltage on the contact pad. One or more conductive structures directly couple the metal grid to a contact pad. The conductive structures may bypass a front side of the image sensor. A bias voltage on the metal grid may be varied through the contact pad whereby a trade-off between reducing cross-talk and increasing quantum efficiency may be adjusted dynamically in accordance with the application of the image sensor, its environment of use, or its mode of operation.

Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the first portion and the second portion of the gate electrode.

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. The first IC die includes a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate. A plurality of electrical coupling structures is arranged at the peripheral region of the first semiconductor device and the second semiconductor device. The plurality of electrical coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupled to the first semiconductor device through a stack of wiring layers and inter-wire vias.