Abstract: A method and circuit for generating a train of synthesized sync pulses in accordance with the Bresenham algorithm in response to an input clock having frequency Fi, such that the leading edges of the pulses occur at least nearly periodically, with time-averaged frequency at least nearly equal to (A/T)Fi, where A and T are integers, and such that the accumulated error, between the actual time interval between the first and last leading edges of Z consecutive ones of the pulses and the time ZT/(AFi), never exceeds 1/Fi. When Fi is equal to (T/A)Fo, where Fo is a predetermined output line frequency, an embodiment of the sync pulse generator includes an accumulator which stores a Count value, a comparator, and logic circuitry for generating the sync pulse train in response to a binary signal asserted by the comparator (and typically also control data that determines a configuration of the logic circuitry).

Abstract: A circuit for providing an overlay in a window on a computer output display including scaling circuitry, storage circuitry for receiving a plurality of lines of source data, input circuitry for loading the storage circuitry in a first prefill mode and in a second low water mark mode, and circuitry for selecting a mode for loading the storage circuitry responsive to the characteristics of the demand for data placed on the storage circuitry.