Patents by Inventor Duncan Collier

Duncan Collier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated clock and power distribution
    Patent number: 7847408
    Abstract: An integrated clock and power distribution network in a semiconductor device includes assigning a first tile to a location on a placement grid corresponding to a top metal layer. An orientation is assigned to the first tile relative to the top metal layer placement grid. The first tile is placed on a representation corresponding to the top metal layer in accordance with the assignments. A second tile is assigned to a location on a placement grid corresponding to a top-1 metal layer. The orientation is assigned to the second tile relative to the top-1 metal layer placement grid. The second tile is placed on a representation corresponding to the top-1 metal layer in accordance with the assignments. The first and second tile are arranged as a full-dense-mesh distribution structure. The first tile includes an integrated clock and power distribution structure. The second tile includes a low impedance underpass structure.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: December 7, 2010
    Assignee: Oracle America, Inc.
    Inventors: Robert P. Masleid, Duncan Collier
  • INTEGRATED CLOCK AND POWER DISTRIBUTION
    Publication number: 20100181685
    Abstract: An integrated clock and power distribution network in a semiconductor device includes assigning a first tile to a location on a placement grid corresponding to a top metal layer. An orientation is assigned to the first tile relative to the top metal layer placement grid. The first tile is placed on a representation corresponding to the top metal layer in accordance with the assignments. A second tile is assigned to a location on a placement grid corresponding to a top-1 metal layer. The orientation is assigned to the second tile relative to the top-1 metal layer placement grid. The second tile is placed on a representation corresponding to the top-1 metal layer in accordance with the assignments. The first and second tile are arranged as a full-dense-mesh distribution structure. The first tile includes an integrated clock and power distribution structure. The second tile includes a low impedance underpass structure.
    Type: Application
    Filed: January 16, 2009
    Publication date: July 22, 2010
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Robert P. Masleid, Duncan Collier, Umesh Gajanan Nawathe, James Ballard