Abstract: Systems and methods for providing collision detection in a memory system including a memory system for storing and retrieving data for a processing system. The memory system includes resource scheduling conflict logic for monitoring one or more memory resources for detecting resource scheduling conflicts. The memory system also includes error reporting logic for generating an error signal in response to detecting a resource scheduling conflict at one or more of the memory resources.

Abstract: Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.

Abstract: A synchronous input to output protocol translator supporting multiple reference oscillator frequencies and fixed latency data computation and chip crossing circuits enables implementation of a method for delaying osc2 relative to osc1 in a configurable way to provide a constant, minimal Tptcc over a range of refosc frequencies between circuits for data transferred. It requires that the data transferred from a register R1 be sent over multiple wires via configurable delay circuitry for osc2, capture circuitry at the input to R2, and a circuit to transfer a synchronizing signal from a non-delayed clock domain to a delayed clock domain. Relative to osc1, osc2 is a delayed, synchronous clock.

Abstract: A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.

Abstract: A memory interface device uses a driver impedance adjustment engine with state machine for off chip driver (OCD) calibration which is used to set the driver voltage levels of the DRAM memory module or DIMM of the JEDEC DDR-II standard type. By adjusting the pull-up drive strength and pull-down drive strength, the output voltage levels and the rise times can be optimized to find the minimal signal swing that is still immune to noise, while not degrading the data eye significantly. The state machine finds the optimal setting for the DRAM Driver Impedance, using both DC and AC methods adjusting the value of the driver impedance through a master ASIC, and then sampling the known value sent back from the DRAM. The state machine will stop when the optimal value of the driver impedance is found and automates the process of detecting the optimal driver impedance and configuring the DRAM module or DIMM accordingly.

Abstract: A memory interface device uses a driver impedance adjustment engine with state machine for off chip driver (OCD) calibration which is used to set the driver voltage levels of the DRAM memory module or DIMM of the JEDEC DDR-II standard type. By adjusting the pull-up drive strength and pull-down drive strength, the output voltage levels and the rise times can be optimized to find the minimal signal swing that is still immune to noise, while not degrading the data eye significantly. The state machine finds the optimal setting for the DRAM Driver Impedance, using both DC and AC methods adjusting the value of the driver impedance through a master ASIC, and then sampling the known value sent back from the DRAM. The state machine will stop when the optimal value of the driver impedance is found and automates the process of detecting the optimal driver impedance and configuring the DRAM module or DIMM accordingly.