Abstract: A signal conditioning circuit contains an oscillator which is connected to the inputs of two mixers. The output of one mixer is coupled, so as to form a feedback path, to a frequency divider circuit whose first output is coupled to the second input of the first mixer. A second signal output of the frequency divider circuit carries a signal with a phase shift of 90 degrees with respect to the signal at the first signal output of the frequency divider circuit. The second signal is supplied to a second input of the second mixer. Feedback results in undesirable signal components in the in-phase and quadrature components being suppressed. At the same time, the in-phase and quadrature components have a fixed phase relationship with respect to one another. The signal conditioning circuit allows desired non-integer division ratios to be achieved.

Abstract: An arrangement for testing a plurality of capacitances in a capacitance array of an integrated circuit includes a power supply and a means for cyclically charging and discharging at least one of the capacitances. In this arrangement, the cycle frequency is dependent on the value of the capacitance. The cycle frequency or a quantity characteristic associated therewith is measured by a means to ascertain a value of the capacitance under test.

Abstract: A VCO circuit (20) has a coil (21) and, in parallel therewith, a constant capacitance (24) and adjustable capacitance elements (22, 23). A first capacitance element (22) is formed by one or more varactors whose capacitance can be adjusted by an analogue adjusting voltage (Vtune), while a second capacitance element (23) is formed by an arrangement comprising a plurality of capacitors which can be actuated by a digital bit word VCWD[N:1]. Digital calibration for the VCO (20) is performed by determining whether the present adjusting voltage is within a particular voltage range and, if this is not the case, the digital bit word being incremented or decremented by a bit value.

Abstract: The invention is directed to a tunable, capacitive component that includes a pair of MOS transistors whose gate connections are connected via a respective coupling capacitance to a pair of circuit nodes between which the tuned capacitance can be tapped off. The four load connections of the MOS transistors are connected to one another. In addition, a tuning input and a reference signal input are provided that are both coupled to the transistor pair. In this arrangement, the reference signal input is designed for setting the operating point of the transistors. The tunable capacitance has a large tuning range and also a low series resistance and permits good linearity properties on account of the operating point setting. The component can be used advantageously in LC oscillators.