Abstract: A processing circuit for a sync signal includes a trial circuit and a windowing circuit. The trial circuit includes a counter that generates a count value proportional to the duration between successive sync pulses. When the count value reaches a trial sync spacing count value, a trial window signal is created and the counter is reset. If a predetermined number of subsequent sync pulses occur within the trial window signal, the sync spacing count value is confirmed and stored in a sync spacing register. The windowing circuit includes a counter that generates a count value proportional to the duration between successive window signals, and compares the count value to the value stored in the sync spacing register to generate a window signal. The window signal is compared with the sync signal pass valid sync signals.

Abstract: A video processing system and method are provided for generating clock and timing signals from an incoming video signal. The system includes a timing reference circuit for generating a reference clock signal, a video format detector coupled to the reference clock signal and to synchronization data derived from the incoming video signal for generating a format signal indicating the format of the incoming video signal, and a clock and timing generator circuit coupled to the format signal and the reference clock signal for generating clock and timing signals that emulate the incoming video signal, and may be locked to the incoming video signal.