Patents by Inventor Dwayne Kreipl

Dwayne Kreipl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8076673
    Abstract: A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the laterally spaced source and drain regions are optionally formed adjacent the recess. Programming of the recessed dielectric antifuse is performed by application of power to the gate and at least one of the source region and the drain region to breakdown the dielectric, which minimizes resistance between the gate and the channel.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: December 13, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Dwayne Kreipl
  • Publication number: 20110089702
    Abstract: A fluidkinetic energy converter includes a passageway-filled enclosure. Turbines are mounted in the passageways and fluid flow may be concentrated on subparts of the turbines by inner fluid flow deflectors or dividers. The energy converter enclosure can include dividers at both inlets and outlets in order to be adaptable for either river or tidal environments. Notably, apart from the turbines and energy generating components, the enclosure may be implemented such as to have no moving parts, thereby reducing complexity, cost, and weight.
    Type: Application
    Filed: December 22, 2010
    Publication date: April 21, 2011
    Inventors: David Boren, Jonathan Boren, Dwayne Kreipl
  • Publication number: 20100308407
    Abstract: A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the laterally spaced source and drain regions are optionally formed adjacent the recess. Programming of the recessed dielectric antifuse is performed by application of power to the gate and at least one of the source region and the drain region to breakdown the dielectric, which minimizes resistance between the gate and the channel.
    Type: Application
    Filed: August 13, 2010
    Publication date: December 9, 2010
    Inventor: Dwayne Kreipl
  • Patent number: 7833860
    Abstract: A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the laterally spaced source and drain regions are optionally formed adjacent the recess. Programming of the recessed dielectric antifuse is performed by application of power to the gate and at least one of the source region and the drain region to breakdown the dielectric, which minimizes resistance between the gate and the channel.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: November 16, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Dwayne Kreipl
  • Patent number: 7795094
    Abstract: A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the laterally spaced source and drain regions are optionally formed adjacent the recess. Programming of the recessed dielectric antifuse is performed by application of power to the gate and at least one of the source region and the drain region to breakdown the dielectric, which minimizes resistance between the gate and the channel.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: September 14, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Dwayne Kreipl
  • Publication number: 20060263946
    Abstract: A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the laterally spaced source and drain regions are optionally formed adjacent the recess. Programming of the recessed dielectric antifuse is performed by application of power to the gate and at least one of the source region and the drain region to breakdown the dielectric, which minimizes resistance between the gate and the channel.
    Type: Application
    Filed: July 25, 2006
    Publication date: November 23, 2006
    Inventor: Dwayne Kreipl
  • Publication number: 20060046354
    Abstract: A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the laterally spaced source and drain regions are optionally formed adjacent the recess. Programming of the recessed dielectric antifuse is performed by application of power to the gate and at least one of the source region and the drain region to breakdown the dielectric, which minimizes resistance between the gate and the channel.
    Type: Application
    Filed: September 2, 2004
    Publication date: March 2, 2006
    Inventor: Dwayne Kreipl
  • Patent number: 5940052
    Abstract: A current measuring circuit for a field emission display includes a testing circuit coupled between a high voltage testing source and the display. The testing circuit includes a sampling circuit formed from a sampling impedance coupled in parallel with a high isolation switch. In one embodiment, the sample circuit is on the high voltage side of the testing source. In another embodiment, the sampling circuit is on the return (low voltage) side of the testing source. In normal operation, the switch is closed to provide the testing voltage directly to the display. During testing, the switch is open so that current flows through the sampling impedance. A sensing circuit coupled to the output of the sampling impedance determines a voltage change in response to opening of the switch. In response to a sensed voltage change, a microprocessor-based controller computes the current drawn by the display.
    Type: Grant
    Filed: January 15, 1997
    Date of Patent: August 17, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Zhong-Yi Xia, Dwayne Kreipl, Glenn Piper