Patents by Inventor Dwight L. Daniels
Dwight L. Daniels has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9598280Abstract: A device in which an electronic circuit positioned within a cavity of a package housing is encased by a bubble restrictor material, with a media resistant material overlaying the bubble restrictor material. The bubble restrictor material functions to inhibit the formation and growth of moisture-related bubbles within the material, including at the interfaces of the material and surfaces within the package housing. The media resistant material is resistant to physical and chemical alterations by media within an external environment to which the device is exposed. The media resistant material and bubble resistant material function to transfer a sensed characteristic of the media to the electronic circuit.Type: GrantFiled: November 10, 2014Date of Patent: March 21, 2017Assignee: NXP USA, Inc.Inventors: Akhilesh K. Singh, Dwight L. Daniels, Darrel R. Frear, Stephen R. Hooper
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Patent number: 9455216Abstract: A structure to improve saw singulation quality and wettability of integrated circuit packages (140) is assembled with lead frames (112) having half-etched recesses (134) in leads. In one embodiment, the structure is a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the lead frame strip. In another embodiment, the structure is a semiconductor device package (140) that includes a semiconductor device encapsulated in a package body (142) having a plurality of leads (120). Each lead has an exposed portion external to the package. There is recess (134) at a corner of each lead. Each recess has a generally concave configuration. Each recess is filled with a removable material (300).Type: GrantFiled: April 27, 2015Date of Patent: September 27, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Dwight L. Daniels, Stephen R. Hooper, Alan J. Magnus, Justin E. Poarch
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Patent number: 9443782Abstract: A method for protecting terminal elements on a wafer during wafer level fabrication processes entails applying a protective coating to the terminal elements prior to further processing operations. These processing operations may include back side grinding of the wafer and/or saw-to-reveal operations to expose the terminal elements from a cap wafer of a wafer structure. The protective coating can protect the terminal elements from potentially damaging contaminants, such as debris from the grinding or saw-to-reveal operations. Furthermore, the protective coating can protect the bond pads from coming into contact with a rapidly oxidizing environment when exposed to water. The protective coating may be a hot-water soluble thermoplastic material the melts from a solid form to a liquid form at a relatively low temperature to enable application of the protective coating in liquid form onto the terminal elements and clean removal of the protective coating from the terminal elements.Type: GrantFiled: August 11, 2015Date of Patent: September 13, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Robert F. Steimle, Dwight L. Daniels, Veera M. Gunturu
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Publication number: 20160130136Abstract: A device in which an electronic circuit positioned within a cavity of a package housing is encased by a bubble restrictor material, with a media resistant material overlaying the bubble restrictor material. The bubble restrictor material functions to inhibit the formation and growth of moisture-related bubbles within the material, including at the interfaces of the material and surfaces within the package housing. The media resistant material is resistant to physical and chemical alterations by media within an external environment to which the device is exposed. The media resistant material and bubble resistant material function to transfer a sensed characteristic of the media to the electronic circuit.Type: ApplicationFiled: November 10, 2014Publication date: May 12, 2016Inventors: AKHILESH K. SINGH, DWIGHT L. DANIELS, DARREL R. FREAR, STEPHEN R. HOOPER
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Publication number: 20150228560Abstract: A structure to improve saw singulation quality and wettability of integrated circuit packages (140) is assembled with lead frames (112) having half-etched recesses (134) in leads. In one embodiment, the structure is a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the lead frame strip. In another embodiment, the structure is a semiconductor device package (140) that includes a semiconductor device encapsulated in a package body (142) having a plurality of leads (120). Each lead has an exposed portion external to the package. There is recess (134) at a corner of each lead. Each recess has a generally concave configuration. Each recess is filled with a removable material (300).Type: ApplicationFiled: April 27, 2015Publication date: August 13, 2015Inventors: Dwight L. DANIELS, Stephen R. HOOPER, Alan J. MAGNUS, Justin E. POARCH
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Patent number: 9093436Abstract: A structure and method to improve saw singulation quality and wettability of integrated circuit packages (140) assembled with lead frames (112) having half-etched recesses (134) in leads. A method of manufacturing lead frames includes providing a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the lead frame strip.Type: GrantFiled: August 7, 2014Date of Patent: July 28, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Dwight L. Daniels, Stephen R. Hooper, Alan J. Magnus, Justin E. Poarch
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Patent number: 9070669Abstract: Methods of manufacturing a flat-pack no-lead microelectronic package (2100) coat exposed base metal at a cut end of a lead frame of the package with solder (1001). One method coats the exposed base metal with solder when the package is in a strip (200, 300). Another method coats the exposed base metal with solder after the package is singulated. As a result, all portions of leads of the package that may receive solder during mounting of the package to a printed circuit board are solder wettable. A solder wettable lead end (504) on the package facilitates formation of a solder fillet during mounting of the package.Type: GrantFiled: November 9, 2012Date of Patent: June 30, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Dwight L. Daniels, Alan J. Magnus, Pamela A. O'Brien
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Publication number: 20140338956Abstract: A structure and method to improve saw singulation quality and wettability of integrated circuit packages (140) assembled with lead frames (112) having half-etched recesses (134) in leads. A method of manufacturing lead frames includes providing a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the lead frame strip.Type: ApplicationFiled: August 7, 2014Publication date: November 20, 2014Inventors: Dwight L. DANIELS, Stephen R. HOOPER, Alan J. MAGNUS, Justin E. POARCH
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Patent number: 8841758Abstract: A structure and method to improve saw singulation quality and wettability of integrated circuit packages (140) assembled with lead frames (112) having half-etched recesses (134) in leads. A method of forming a semiconductor device package includes providing a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the strip.Type: GrantFiled: June 29, 2012Date of Patent: September 23, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Dwight L. Daniels, Stephen R. Hooper, Alan J. Magnus, Justin E. Poarch
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Publication number: 20140134799Abstract: Methods of manufacturing a flat-pack no-lead microelectronic package (2100) coat exposed base metal at a cut end of a lead frame of the package with solder (1001). One method coats the exposed base metal with solder when the package is in a strip (200, 300). Another method coats the exposed base metal with solder after the package is singulated. As a result, all portions of leads of the package that may receive solder during mounting of the package to a printed circuit board are solder wettable. A solder wettable lead end (504) on the package facilitates formation of a solder fillet during mounting of the package.Type: ApplicationFiled: November 9, 2012Publication date: May 15, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Dwight L. DANIELS, Alan J. MAGNUS, Pamela A. O'BRIEN
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Publication number: 20140001616Abstract: A structure and method to improve saw singulation quality and wettability of integrated circuit packages (140) assembled with lead frames (112) having half-etched recesses (134) in leads. A method of forming a semiconductor device package includes providing a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the strip.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Dwight L. DANIELS, Stephen R. HOOPER, Alan J. MAGNUS, Justin E. POARCH
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Patent number: 8476087Abstract: Fabrication methods are provided for a sensor device packages. An exemplary fabrication method involves bonding a sensor structure and another structure using a sealing structure. The sealing structure surrounds a diaphragm region of the sensor structure and provides an airtight seal between the sensor structure and the other structure to establish a fixed reference pressure on one side of the diaphragm region.Type: GrantFiled: April 21, 2011Date of Patent: July 2, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Stephen R. Hooper, Dwight L. Daniels, James D. MacDonald, William G. McDonald, Chunlin C. Xia
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Patent number: 8384168Abstract: Apparatus and related fabrication methods are provided for a sensor device. The sensor device includes a sensor structure including a first portion having a sensing arrangement formed thereon and a second structure. A sealing structure is interposed between the sensor structure and the second structure, wherein the sealing structure surrounds the first portion of the sensor structure. The sealing structure establishes a fixed reference pressure on a first side of the first portion, and an opposing side of the first portion is exposed to an ambient pressure.Type: GrantFiled: April 21, 2011Date of Patent: February 26, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Stephen R. Hooper, Dwight L. Daniels, James D. MacDonald, William G. McDonald, Chunlin C. Xia
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Patent number: 8378433Abstract: A semiconductor device includes a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. The second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. A vacuum sealing layer is formed over the first cap wafer, wherein the sealing layer vacuum seals the first opening.Type: GrantFiled: June 14, 2011Date of Patent: February 19, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Scott M. Hayes, Dwight L. Daniels
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Publication number: 20120266684Abstract: Apparatus and related fabrication methods are provided for a sensor device. The sensor device includes a sensor structure including a first portion having a sensing arrangement formed thereon and a second structure. A sealing structure is interposed between the sensor structure and the second structure, wherein the sealing structure surrounds the first portion of the sensor structure. The sealing structure establishes a fixed reference pressure on a first side of the first portion, and an opposing side of the first portion is exposed to an ambient pressure.Type: ApplicationFiled: April 21, 2011Publication date: October 25, 2012Applicant: Freescale Semiconductor, Inc.Inventors: Stephen R. Hooper, Dwight L. Daniels, James D. MacDonald, William G. McDonald, Chunlin C. Xia
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Publication number: 20120270354Abstract: Fabrication methods are provided for a sensor device packages. An exemplary fabrication method involves bonding a sensor structure and another structure using a sealing structure. The sealing structure surrounds a diaphragm region of the sensor structure and provides an airtight seal between the sensor structure and the other structure to establish a fixed reference pressure on one side of the diaphragm region.Type: ApplicationFiled: April 21, 2011Publication date: October 25, 2012Applicant: Freescale Semiconductor, Inc.Inventors: Stephen R. Hooper, Dwight L. Daniels, James D. MacDonald, William G. McDonald, Chunlin C. Xia
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Publication number: 20110241181Abstract: A semiconductor device includes a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. The second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. A vacuum sealing layer is formed over the first cap wafer, wherein the sealing layer vacuum seals the first opening.Type: ApplicationFiled: June 14, 2011Publication date: October 6, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: SCOTT M. HAYES, DWIGHT L. DANIELS
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Patent number: 7985659Abstract: A method for forming a semiconductor device includes providing a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. After the providing the first cap wafer and second cap wafer, the second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. After the bonding the second cap wafer to the device wafer, a vacuum is applied, wherein during the applying the vacuum, a sealing layer is formed over the first cap wafer, wherein the sealing layer seals the first opening.Type: GrantFiled: March 31, 2010Date of Patent: July 26, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Scott M. Hayes, Dwight L. Daniels
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Patent number: 6303978Abstract: An optical semiconductor component includes a semiconductor substrate (120) and a packaging material (140) located over the semiconductor substrate. The packaging material includes an optically transparent cycloaliphatic polymer (142, 242, 400, 600). A method of manufacturing the component includes nixing a monomer (300, 500) of the polymer with a catalyst to form the packaging material, filtering the packaging material, applying the packaging material, and curing the packaging material.Type: GrantFiled: July 27, 2000Date of Patent: October 16, 2001Assignee: Motorola, Inc.Inventors: Dwight L. Daniels, Treliant Fang, Athena M. Parmenter
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Patent number: 6201186Abstract: An electronic component assembly (10) is formed by mounting an electronic component (15) to the leads (12) of a leadframe (18). The portions of the leadframe (18) that come in physical contact with the electronic component (15) are electrically connected to the electronic component with bonding wires (31) or by placing the bonding regions (30) of the electronic component (15) in direct physical contact with the tips (35) of the leads (12). A package (20) is used to encapsulate the leads (12) and the electronic component (15).Type: GrantFiled: June 29, 1998Date of Patent: March 13, 2001Assignee: Motorola, Inc.Inventors: Dwight L. Daniels, Jeffrey A. Miks, Dilip Patel