Patents by Inventor Dyson Wilkes
Dyson Wilkes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240142572Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.Type: ApplicationFiled: December 20, 2023Publication date: May 2, 2024Inventors: Dian Tresna Nugraha, Markus Bichl, Dyson Wilkes
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Patent number: 11906654Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.Type: GrantFiled: July 13, 2021Date of Patent: February 20, 2024Assignee: Infineon Technologies AGInventors: Dian Tresna Nugraha, Markus Bichl, Dyson Wilkes
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Publication number: 20230138972Abstract: In some methods, sampled values based on a reception signal are stored in rows and columns of a memory array. A first 1-dimensional (1D) detector is moved in a first direction over the memory array. The first 1D detector includes a first cell under test and first and second training cells on opposite sides of the first cell under test. The first cell under test and the first and second training cells of the first 1D detector being aligned in the first direction. A second 1D detector is moved over the memory array. The second 1D detector includes a second cell under test and third and fourth training cells on opposite sides of the second cell under test. The second cell under test and the third and fourth training cells of the second 1D detector are aligned in a second direction that is perpendicular to the first direction.Type: ApplicationFiled: October 28, 2021Publication date: May 4, 2023Inventors: Ajayan Vijayakumaran Nair, David Michael Addison, Markus Bichl, Moustafa Samy Abdelkhalek Ahmed Emara, Andre Roger, Dyson Wilkes
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Patent number: 11354181Abstract: A fault detector for detecting a fault in a digital processing circuit configured to transform an input data set to an output data set based on an energy conserving function. The fault detector includes an input sum of absolute squares circuit configured to determine an input sum of absolute squares value of the input data set, which has a predetermined length; an output sum of absolute squares circuit configured to determine an output sum of absolute squares value of the output data set; and an energy conservation check circuit configured to identify a fault in the digital processing circuit if a comparison based on the input sum of absolute squares value and the output sum of absolute squares value does not meet a predetermined energy conservation criteria.Type: GrantFiled: March 23, 2020Date of Patent: June 7, 2022Assignee: Infineon Technologies AGInventors: Dyson Wilkes, Siva Karteek Bolisetti
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Publication number: 20220018933Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.Type: ApplicationFiled: July 13, 2021Publication date: January 20, 2022Inventors: Dian Tresna Nugraha, Markus Bichl, Dyson Wilkes
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Publication number: 20210294688Abstract: A fault detector for detecting a fault in a digital processing circuit configured to transform an input data set to an output data set based on an energy conserving function. The fault detector includes an input sum of absolute squares circuit configured to determine an input sum of absolute squares value of the input data set, which has a predetermined length; an output sum of absolute squares circuit configured to determine an output sum of absolute squares value of the output data set; and an energy conservation check circuit configured to identify a fault in the digital processing circuit if a comparison based on the input sum of absolute squares value and the output sum of absolute squares value does not meet a predetermined energy conservation criteria.Type: ApplicationFiled: March 23, 2020Publication date: September 23, 2021Inventors: Dyson Wilkes, Siva Karteek Bolisetti
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Patent number: 7895416Abstract: A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements with a plurality of controller elements achieve this. In a preferred embodiment the integrated circuit includes a plurality of processing blocks, which interface to a reconfigurable interconnection means. A processing block has two forms, namely a shared resource block and a dedicated resource block. Each processing block consists of one or a plurality of controller elements and a plurality of processing elements. The controller element and processing element generally comprise diverse rigid coarse and fine grained circuits and are interconnected through dedicated and reconfigurable interconnect. The processing blocks can be configured as a hierarchy of blocks and or fractal architecture.Type: GrantFiled: June 24, 2009Date of Patent: February 22, 2011Assignee: Akya (Holdings) LimitedInventors: Graeme Roy Smith, Dyson Wilkes
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Publication number: 20090259824Abstract: A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements with a plurality of controller elements achieve this. In a preferred embodiment the integrated circuit includes a plurality of processing blocks, which interface to a reconfigurable interconnection means. A processing block has two forms, namely a shared resource block and a dedicated resource block. Each processing block consists of one or a plurality of controller elements and a plurality of processing elements. The controller element and processing element generally comprise diverse rigid coarse and fine grained circuits and are interconnected through dedicated and reconfigurable interconnect. The processing blocks can be configured as a hierarchy of blocks and or fractal architecture.Type: ApplicationFiled: June 24, 2009Publication date: October 15, 2009Applicant: AKYA (HOLDINGS) LIMITEDInventors: Graeme Roy SMITH, Dyson WILKES
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Patent number: 7571303Abstract: A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements with a plurality of controller elements achieve this. In a preferred embodiment the integrated circuit includes a plurality of processing blocks, which interface to a reconfigurable interconnection means. A processing block has two forms, namely a shared resource block and a dedicated resource block. Each processing block consists of one or a plurality of controller elements and a plurality of processing elements. The controller element and processing element generally comprise diverse rigid coarse and fine grained circuits and are interconnected through dedicated and reconfigurable interconnect. The processing blocks can be configured as a hierarchy of blocks and or fractal architecture.Type: GrantFiled: January 31, 2007Date of Patent: August 4, 2009Assignee: AKYA (Holdings) LimitedInventors: Graeme Roy Smith, Dyson Wilkes
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Patent number: 7516372Abstract: A processor control system allows stored program code to be replaced. The original code can be stored entirely in a first memory, for example a ROM, with correction instructions stored in a second memory, for example a RAM, and the second memory is accessed only when a correction instruction exits. Received memory addresses are divided into a first plurality of most significant bits, and a second plurality of least significant bits. Only when the second plurality of least significant bits are all equal to zero, and there is a correction instruction stored in the RAM with an address which equals the most significant bits, the correction instruction is read and supplied to the processor. This, employs relatively little additional hardware, and the efficiency of the system is improved.Type: GrantFiled: January 27, 2003Date of Patent: April 7, 2009Assignee: Microsoft CorporationInventor: Dyson Wilkes
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Patent number: 7061272Abstract: A finite state machine (FSM) circuit including a random access memory (RAM) as the basic logical element and a multiplexer, which can be programmed to perform arbitrary sequences of events. The RAM is used as a state table and output states are fed back to determine the next memory location. The number of locations in the RAM is reduced in comparison with prior art devices, which minimises power consumed by a microprocessor implementing such an FSM. This reduction in the number of locations is possible because only relevant inputs to the RAM are selected. The circuit has both synchronous and asynchronous implementations.Type: GrantFiled: June 30, 2004Date of Patent: June 13, 2006Assignee: Infineon Technologies AGInventors: Dyson Wilkes, Kostas Spyridis
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Publication number: 20050240823Abstract: A processor control system allows stored program code to be replaced. The original code can be stored entirely in a first memory, for example a ROM, with correction instructions stored in a second memory, for example a RAM, and the second memory is accessed only when a correction instruction exits. Received memory addresses are divided into a first plurality of most significant bits, and a second plurality of least significant bits. Only when the second plurality of least significant bits are all equal to zero, and there is a correction instruction stored in the RAM with an address which equals the most significant bits, the correction instruction is read and supplied to the processor. This, employs relatively little additional hardware, and the efficiency of the system is improved.Type: ApplicationFiled: January 27, 2003Publication date: October 27, 2005Inventor: Dyson Wilkes
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Publication number: 20050140390Abstract: A finite state machine (FSM) circuit including a random access memory (RAM) as the basic logical element and a multiplexer, which can be programmed to perform arbitrary sequences of events. The RAM is used as a state table and output states are fed back to determine the next memory location. The number of locations in the RAM is reduced in comparison with prior art devices, which minimises power consumed by a microprocessor implementing such an FSM. This reduction in the number of locations is possible because only relevant inputs to the RAM are selected. The circuit has both synchronous and asynchronous implementations.Type: ApplicationFiled: June 30, 2004Publication date: June 30, 2005Inventors: Dyson Wilkes, Kostas Spyridis