Abstract: A compiler-directed speculative approach to resolve performance-degrading long latency events in an application is described. One or more performance-degrading instructions are identified from multiple instructions to be executed in a program. A set of instructions prefetching the performance-degrading instruction is defined within the program. Finally, at least one speculative bit of each instruction of the identified set of instructions is marked to indicate a predetermined execution of the instruction.

Abstract: A method for an allocation of stacked registers for Intel's Itanium® processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a plurality of procedures. In step II, the disclosed method performs an inter-procedural analysis to assign quota of stacked register usage to every procedure. In step III, each procedure is allocated stacked register usage based on the quota assignments of step II.

Abstract: A ? function provides a mechanism for static single assignment in the presence of predicated code. Guards placed on each source operand of the ? function indicate the condition under which the corresponding source operand is live and provide correct materialization of the ? functions after code reordering. For control functions ?c representing a confluence of live reaching definitions at a join point in the control flow graph, the guards indicate the basic block which is the source of the edge associated with the source operand. The ?c operands are paired with the source basic block of the incoming edge(s) along which they are live. The operands are also ordered according to a topological ordering of their associated block. This ordering is maintained through subsequent code transformations. In the topological ordering, the source of the edge from which the definition was passed is defined.

Abstract: Code restructuring or reordering based on profiling information and memory hierarchy is provided by constructing a Program Execution Graph (PEG) corresponding to a level of the memory hierarchy, partitioning this PEG to reduce estimated memory overhead costs below an upper bound, and constructing a PEG for a next level of the memory hierarchy from the partitioned PEG. The PEG is constructed from control flow and frequency information from a profile of the program to be restructured. The PEG is a weighted undirected graph comprising nodes representing basic blocks and edges representing transfer of control between pairs of basic blocks. The weight of a node is the size of the basic block it represents and the weight of an edge is the frequency of transition between the pair of basic blocs it connects.

Abstract: Methods and apparatus for preserving precise exceptions in code reordering by using control speculation are disclosed. A disclosed system uses a control speculation module to reorder instructions within an application program and preserve precise exceptions. Instructions, excepting and non-excepting, can be reordered by the control speculation module if the instructions meet certain conditions. When an excepting instruction is reordered, a check instruction is inserted into the program execution path and a recovery block is generated. The check instruction determines if the reordered excepting instruction actually needs to generate an exception. The recovery block contains instructions to revert the effects of code reordering. If the check instruction detects the need for an exception, the recovery block is executed to restore the architectural state of the processor and the exception is handled.

Abstract: Optimizing compiler performance by applying data speculation within modulo scheduled loops to achieve a higher degree of instruction-level parallelism. The compiler locates a schedule for specifying an order of execution of the instructions and allocates rotating registers for the instruction execution. Based upon the schedule and the register allocation, the compiler determines an initiation interval specifying a number of instruction issue cycles between initiation of successive iterations related to the scheduling of the instructions.

Abstract: A critical load ordering unit is responsible for receiving instructions during a critical phase. Load instructions are associated with the number of instructions during the critical phase that depend on the load instructions. The instructions may then be ordered based on their dependence counts and/or marked as critical load instructions.

Abstract: To make a branch prediction, a branch prediction apparatus determines a trigger load instruction whose value feeds into the branch instruction. A hash value is associated with the branch instruction. The branch prediction apparatus computes the hash value based on the trigger load instruction. If the hash value has not changed, the branch prediction apparatus predicts the branch to be chosen based on past predictions for the hash value.

Abstract: A prefetch engine is responsible for prefetching critical data. The prefetch engine operates when a cache miss occurs accessing critical data requested by a processor. The prefetch engine requests cache lines surrounding the cache line satisfying the data request be loaded into the cache.

Abstract: A &PHgr; function provides a mechanism for static single assignment in the presence of predicated code. Guards placed on each source operand of the &PHgr; function indicate the condition under which the corresponding source operand is live and provide correct materialization of the &PHgr; functions after code reordering. For control functions &PHgr;c representing a confluence of live reaching definitions at a join point in the control flow graph, the guards indicate the basic block which is the source of the edge associated with the source operand. The &PHgr;c operands are paired with the source basic block of the incoming edge(s) along which they are live. The operands are also ordered according to a topological ordering of their associated block. This ordering is maintained through subsequent code transformations. In the topological ordering, the source of the edge from which the definition was passed is defined.

Abstract: The critical cache tracks a critical score for each cache line in the critical cache. On cache hits, the critical score of the hit cache line is incremented by an instance score assigned to the data request. On cache misses, data may be retrieved from main memory without allocating a cache line into the critical cache, in which case the instance score is subtracted from the critical scores of all cache lines in the cache. Alternatively on a cache miss, the cache line with the smallest critical score is removed from the cache. The smallest critical score is then subtracted from each cache line in the critical cache. A new cache line is allocated that satisfies the data request, and the new cache line is given the instance score of the data request as a critical score.

Abstract: We disclose a function unit based finite state automata data structure for use in computer program compilers. According to an aspect of an embodiment, the data structure comprises a function unit vector, having no more used bits than there are issue ports for any particular microprocessor, and a plurality of valid template assignments for each function unit vector. In a preferred embodiment, the template assignments are constructed so as to account for dispersal rules associated with the particular microprocessor. Further, the template assignments can be sorted according to priority data.

Abstract: A compiler comprising an integrated instruction scheduler and resource management system is provided. According to an aspect of an embodiment, the resource management system includes a function unit based finite state automata system. Instructions to be compiled are modeled through the function unit based finite state automata system based on their function unit usage, before they are emitted as compiled computer code. We also disclose a function unit based finite state automata data structure and computer implemented methods for making the same.

Abstract: A compiler-directed speculative approach to resolve performance-degrading long latency events in an application is described. One or more performance-degrading instructions are identified from multiple instructions to be executed in a program. A set of instructions prefetching the performance-degrading instruction is defined within the program. Finally, at least one speculative bit of each instruction of the identified set of instructions is marked to indicate a predetermined execution of the instruction.

Abstract: To make a branch prediction, a branch prediction apparatus determines a trigger load instruction whose value feeds into the branch instruction. A hash value is associated with the branch instruction. The branch prediction apparatus computes the hash value based on the trigger load instruction. If the hash value has not changed, the branch prediction apparatus predicts the branch to be chosen based on past predictions for the hash value.

Abstract: A method and system for scheduling computer instructions for execution as part of a compilation process in which an original computer program that defines a set of operations is compiled to produce an executable program. The method may schedule instructions in a different execution order from the order defined by the original computer program. When certain instructions are scheduled to execute before other instructions which they followed in the original computer program, the executable program that results may produce a different operational behavior than the operational behavior defined by the original computer program. The method inserts additional instructions so that an executable program that includes instructions scheduled to execute before other instructions which they followed in the original computer program produces the same set of operations as defined by the original computer program.

Abstract: An improved technique for incrementally updating a source code representation having cloned variable name definitions to static single assignment (SSA) form is described. The technique receives an intermediate representation of a source program in non-SSA form having one or more cloned variable name definitions that correspond to an original variable name. All the original variable names and their corresponding cloned variable names are collected. An iterative dominance frontier set for those nodes containing a cloned variable name definition or an original variable name definition is formed. This iterative dominance frontier set is then used to determine the nodes in which a single phi-function is inserted for each original variable name. Each use of an original variable name is changed to the cloned variable name that reaches the use. The arguments of the inserted phi-functions are then updated with the cloned variable names that reach the inserted phi-functions.

Abstract: A method and system for detecting and eliminating interferences between resources in SSA-form &phgr;-instructions so that an optimizing compiler can translate optimized SSA-form code back to non-SSA-form code. The method traverses the control flow graph associated with an SSA-form program or routine in order to analyze each &phgr;-instruction within the SSA-form program or routine. All possible pairs of resources associated with each &phgr;-instruction are analyzed for interference. Once all interferences have been detected, the method inserts copy instructions into the SSA-form intermediate-level code program or routine in order to eliminate the interferences.

Abstract: Code restructuring or reordering based on profiling information and memory hierarchy is provided by constructing a Program Execution Graph (PEG) corresponding to a level of the memory hierarchy, partitioning this PEG to reduce estimated memory overhead costs below an upper bound, and constructing a PEG for a next level of the memory hierarchy from the partitioned PEG. The PEG is constructed from control flow and frequency information from a profile of the program to be restructured. The PEG is a weighted undirected graph comprising nodes representing basic blocks and edges representing transfer of control between pairs of basic blocks. The weight of a node is the size of the basic block it represents and the weight of an edge is the frequency of transition between the pair of basic blocks it connects. The nodes of the PEG are partitioned or clustered into clusters such that the sum of the weights of the nodes in any cluster is no greater than an upper bound.

Abstract: FORTRAN WHERE construct compilation and optimization is provided by excluding an assignment statement containing a transformational intrinsic function from loop fusion of the WHERE construct. To perform this loop fusion, intrastatement dependence analysis is performed within each assignment statement of the WHERE construct, and then interstatement dependence analysis is performed between each assignment statement and assignment statements subsequent to the assignment statement. Responsive to this dependence analysis, pairs of assignment statements which may not be fused into a single loop are identified, and non-fusion boundaries between adjacent assignment statements where assignment statements preceding a non-fusion boundary and assignment statements subsequent to the non-fusion boundary may not be fused into a single loop are identified. This fusion analysis yields a loop fusion configuration.