Abstract: A method of designing a logic circuit for implementing a predetermined boolean function defines a binary tree structure formed of transmission gate multiplexer (TGM) circuits. The TGM tree structure includes one binary stage for each input variable. A resulting logic circuit design is reduced by one or more stages to improve performance by employing selected boolean functions of the most significant bits of the input variables as input signals to a reduced tree structure. The method is applicable circuit design in all MOS-type technologies including NMOS, PMOS, CMOS, BiMOS, FET and the like.

Abstract: A multiplexer circuit is formed of two-to-one transmission gate multiplexer (TGM) circuits (80) connected in series. A first stage TGM (80) selects among two of the input variable signals (I0,I1). Each subsequent stage TGM (70) selects among the next preceding stage output signal (81) and another one of the input variable signals (I2). Each TGM is controlled by a unique control signal (S1,S2) so that loading on the control lines is limited to one TGM circuit to improve propagation delay. The series arrangement of TGM circuits can be extended as needed (M3,M4,M5).

Abstract: Transmission gate multiplexer circuits (FIG. 5) are used to form Booth select logic (FIG. 12), Booth recode multiplexer logic (FIG. 11), constant K-bit logic (FIG. 13) and reduced sign bit logic (FIG. 14). In these circuits, input variables are selectively applied both to multiplexer input terminals and to multiplexer select terminals, to achieve the desired logic functions with minimum delay.