Abstract: A receiver front-end includes a first variable-gain amplifier that performs attenuation; a continuous time linear equalizer coupled to the input or output of the first variable-gain amplifier, wherein a combination of the first variable-gain amplifier and the continuous time linear equalizer produces a processed signal; a plurality of track-and-hold circuits that sample the processed signal in an interleaved manner; and a plurality of second variable-gain amplifiers receiving input signals from the plurality of track-and-hold circuits respectively.

Abstract: A receiver front-end includes a first variable-gain amplifier that performs attenuation; a continuous time linear equalizer coupled to the input or output of the first variable-gain amplifier, wherein a combination of the first variable-gain amplifier and the continuous time linear equalizer produces a processed signal; a plurality of track-and-hold circuits that sample the processed signal in an interleaved manner; and a plurality of second variable-gain amplifiers receiving input signals from the plurality of track-and-hold circuits respectively.

Abstract: An attenuator system comprising a variable impedance configured to provide an impedance from among a plurality of impedance states, the variable impedance comprising a first port, a second port, a first transistor comprising first and second channel terminals coupled between the first port and the second port, and a second transistor comprising first and second channel terminals coupled between the first port and the second port, and a control circuit configured to control the variable impedance to a first impedance state of the plurality of impedance states at least in part by providing a first output voltage to a control terminal of the first transistor to turn the first transistor on, wherein the first transistor is configured to operate in an under-driven mode when turned on.

Abstract: An attenuator system comprising a variable impedance configured to provide an impedance from among a plurality of impedance states, the variable impedance comprising a first port, a second port, a first transistor comprising first and second channel terminals coupled between the first port and the second port, and a second transistor comprising first and second channel terminals coupled between the first port and the second port, and a control circuit configured to control the variable impedance to a first impedance state of the plurality of impedance states at least in part by providing a first output voltage to a control terminal of the first transistor to turn the first transistor on, wherein the first transistor is configured to operate in an under-driven mode when turned on.

Abstract: Systems and method for supply noise suppression in electronic circuits are described. The systems described herein may prevent or at least limit noise coupling from a supply line to a load, and may further prevent or at least limit noise generated at the load from coupling to the supply line. The systems and methods described herein may be particularly useful in systems-on-chip with multi-level interposers, in which multiple supply lines are used to provide different voltage levels to the chip. In these systems, in fact, the supply lines can exhibit large impedances, which may in turn promote noise coupling from one circuit to another. In one example, a voltage regulator is provided that includes a linear regulator and an active shunt circuit.

Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.

Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.

Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.

Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.