Patents by Inventor E. R. Hsieh

E. R. Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure and process of basic complementary logic gate made by junctionless transistors
    Publication number: 20120126197
    Abstract: The present invention discloses a structure and process of basic complementary logic gate made by junctionless transistors. Junctionless N-channel transistor(s) and junctionless P-channel transistor(s) are formed on a semiconductor wafer, a conducting contact structure is used to connect the transistors to form a basic complementary logic gate(s) such as inverter, NAND, NOR, etc.
    Type: Application
    Filed: March 9, 2011
    Publication date: May 24, 2012
    Applicant: National Chiao Tung University
    Inventors: Steve S. Chung, E. R. Hsieh