Patents by Inventor Eanonn Byrne

Eanonn Byrne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5668551
    Abstract: Using a power-up delay circuit on an analog/digital converter integrated circuit (i.e., an analog-to-digital converter or a digital-to-analog converter) to generate a signal delayed from power-up, and initiating a calibration of the converter upon detecting the delayed signal. In preferred embodiments, calibration can also be initiated in response to a signal on a calibration input pin of the integrated circuit, and the duration of the delay can be derived from a reference (e.g., by charging an external capacitor with it) or from the duration of a calibration operation. Circuitry can be provided to automatically place the circuit in an operating mode upon power-up that keeps the integrated circuit in shutdown mode when it is not converting or calibrating.
    Type: Grant
    Filed: January 18, 1995
    Date of Patent: September 16, 1997
    Assignee: Analog Devices, Inc.
    Inventors: Patrick J. Garavan, Eanonn Byrne