Patents by Inventor Earl R. Nicewarner, Jr.

Earl R. Nicewarner, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5776797
    Abstract: A three dimensional flexible assembly of integrated circuits and method of fabricating the assembly of circuits including a folded flexible substrate with integrated circuit chips. The invention has provisions for allowing mechanical and electrically functional attachment of integrated circuit chips to one or both sides of the flexible substrate using flip chip assembly techniques. In addition, a rigid package substrate is provided upon which the folded substrate is secured with the associated chips. The chips are electrically connected to the flexible substrate and the flexible substrate is in turn electrically connected to the rigid substrate. A cover is also provided that covers and protects the flexible substrate and the associated chips as well as a portion of the connected rigid package substrate. In an additional embodiment, the cover and rigid substrate are omitted and instead the combined folded flexible substrate and integrated circuit chips are encapsulated with a suitable compound.
    Type: Grant
    Filed: July 2, 1997
    Date of Patent: July 7, 1998
    Assignee: Fairchild Space and Defense Corporation
    Inventors: Earl R. Nicewarner, Jr., Steven L. Frinak
  • Patent number: 5646446
    Abstract: A three dimensional flexible assembly of integrated circuits and method of fabricating the assembly of circuits including a folded flexible substrate with integrated circuit chips. The invention has provisions for allowing mechanical and electrically functional attachment of integrated circuit chips to one or both sides of the flexible substrate using flip chip assembly techniques. In addition, a rigid package substrate is provided upon which the folded substrate is secured with the associated chips. The chips are electrically connected to the flexible substrate and the flexible substrate is in turn electrically connected to the rigid substrate. A cover is also provided that covers and protects the flexible substrate and the associated chips as well as a portion of the connected rigid package substrate In an additional embodiment, the cover and rigid substrate are omitted and instead the combined folded flexible substrate and integrated circuit chips are encapsulated with a suitable compound.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: July 8, 1997
    Assignee: Fairchild Space and Defense Corporation
    Inventors: Earl R. Nicewarner, Jr., Steven L. Frinak
  • Patent number: 5491612
    Abstract: An integrated circuit package that includes three base substrate support members. One base substrate support member is rigid and has two sides and the other two base substrate members are flexible and are located adjacent each side of the rigid base substrate support member. Each flexible base substrate support member has an inner surface and a series of flip chips are located between the inner surfaces of the flexible base substrate support members and the sides of the rigid base substrate support member. The three base substrate support members are electrically connected together and a termination connection is provided at one end of the assembly. In addition, logic chips are provided that are located adjacent the connector for controlling the various flip chips.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: February 13, 1996
    Assignee: Fairchild Space and Defense Corporation
    Inventor: Earl R. Nicewarner, Jr.
  • Patent number: 5327325
    Abstract: An integrated circuit package that permits high density packaging of circuit chips. The integrated circuit package has a base substrate support member with an upper and a lower surface. A cavity is located in its upper surface and a similar cavity is located in its lower surface. Two circuit chips are located in each cavity that are connected together in back to back relationship. The cavities are closed or sealed by lids that are bonded to mounting surfaces that are located on the base substrate support member and surround the cavities. A series of terminating leads are located on two sides of the base substrate support member that are electrically connected to the circuit chips. A single cavity embodiment is also set forth that is designed for use when a lesser density is acceptable or desired.
    Type: Grant
    Filed: February 8, 1993
    Date of Patent: July 5, 1994
    Assignee: Fairchild Space and Defense Corporation
    Inventor: Earl R. Nicewarner, Jr.