Abstract: A communications system includes a first network that includes a plurality of entities and a router. The router includes a network address translator. A node is capable of communicating data units with entities in the first network. Each data unit includes security information, such as information according to the Internet Security Association and Key Management protocol (ISAKMP) and the Encapsulating Security Payload (ESP) protocol. The network address translator is adapted to convert a destination address in a received data unit from the node to an address of one of the entities based on the security information in the received data unit.

Abstract: A communication system includes a data network that is coupled to various nodes, including routers. In one example arrangement, a first router is part of a first local network and a second router is part of a second local network. Each router includes a security gateway module and a keep-alive module. The security gateway module is capable of establishing a secure link, such as one according to an Internet Protocol Security (IPsec) protocol, over the data network. The keep-alive module sends one or more ping messages over the secure link to the remote router (or a node coupled to the router), which responds with appropriate ping replies to indicate that a link is alive.

Abstract: A communications system includes a data network that is coupled to an access system, which enables access to the data network by a client system. The client system issues requests through a router and the access system, with the requests specifying a server system as the destination. The server system sends response messages back to the client system through the data network and the router. The router is capable of modifying an indication of the maximum size of at least a portion of a message. This ensures that response messages communicated by the server system are not too large that the access system is unable to handle the response messages.

Abstract: In one embodiment of the invention, a NAT processor includes a table and a parser. The table stores a plurality of entries for a packet in a sequence of packets of a message transmitted from the first network to the second network. The entries include a first connection identifier corresponding to the first network. The entries are obtained from a description file of the packet. The parser is coupled to the table to parse the sequence of packets using the table. The parser extracts the first connection identifier.

Abstract: A technique for providing a device referred to as a transparent bump between a local area network and a router. The device is inserted with minimal intrusion to the devices on the LAN to provide a certain operation, such as web caching. The device initializes at start-up in the promiscuous mode to learn the MAC address of the router and subsequently accepts data packets destined to the router for internal processing. Accesses to a web page are checked in the device to determine if cached data is present, so that redundant accesses are reduced. The device initializes and performs its intended function transparently to a user on the local area network.

Abstract: A technique for providing a device referred to as a transparent bump between a local area network and a router. The device is inserted with minimal intrusion to the devices on the LAN to provide a certain operation, such as web caching. The device initializes at start-up in the promiscuous mode to learn the MAC address of the router and subsequently accepts data packets destined to the router for internal processing. Accesses to a web page are checked in the device to determine if cached data is present, so that redundant accesses are reduced. The device initializes and performs its intended function transparently to a user on the local area network.

Abstract: A method and apparatus for implementing a 32-bit operating system which supports 16-bit code includes loading basic input output system (BIOS) code into a base portion of a memory and loading first operating system code into the base portion. Second operating system code is then loaded into an extended portion of the memory and the second operating system code is allowed to overwrite the BIOS code and the first operating system code with data.