Patents by Inventor Eashwar Thiagarajan
Eashwar Thiagarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11770109Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.Type: GrantFiled: September 1, 2022Date of Patent: September 26, 2023Assignee: Cypress Semiconductor CorporationInventors: Erhan Hancioglu, Eashwar Thiagarajan, Eric Mann, Harold Kutz, Vaibhav Ramamoorthy, Rajiv Singh, Amsby Richardson, Jr.
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Publication number: 20230188139Abstract: Implementations disclosed describe an integrated circuit (IC) having a plurality of reconfigurable analog circuits that include a finite state machine (FSM) logic circuit and further include an interface to receive an input signal. In a first IC configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the IC may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the FSM logic circuit processing the first output value, the IC may reconfigure the plurality of reconfigurable analog circuits into a second IC configuration having a second configuration setting.Type: ApplicationFiled: December 16, 2022Publication date: June 15, 2023Applicant: Cypress Semiconductor CorporationInventors: Eashwar THIAGARAJAN, Andrew PAGE, Harold KUTZ, Kendall CASTOR-PERRY, Rajiv SINGH, Erhan HANCIOGLU, Bert SULLAM
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Publication number: 20230055860Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.Type: ApplicationFiled: September 1, 2022Publication date: February 23, 2023Applicant: Cypress Semiconductor CorporationInventors: Erhan Hancioglu, Eashwar Thiagarajan, Eric Mann, Harold Kutz, Vaibhav Ramamoorthy, Rajiv Singh, Amsby Richardson, JR.
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Patent number: 11533055Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.Type: GrantFiled: March 29, 2019Date of Patent: December 20, 2022Assignee: Cypress Semiconductor CorporationInventors: Eashwar Thiagarajan, Andrew Page, Harold Kutz, Kendall Castor-Perry, Rajiv Singh, Erhan Hancioglu, Bert Sullam
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Patent number: 11496148Abstract: One or more systems and/or methods for implementing an analog-to-digital converter system with a floating digital channel configuration are provided. An analog input component is configured to receive measured analog signals, and output analog signals, corresponding to the measured analog signals, to an analog channel coupled to the analog input component. The analog channel is coupled to a switching component connected to a first digital channel and a second digital channel. The analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel.Type: GrantFiled: April 28, 2021Date of Patent: November 8, 2022Assignee: Cypress Semiconductor CorporationInventors: Eric N. Mann, Erhan Hancioglu, Eashwar Thiagarajan, Harold Kutz, Amsby D Richardson, Jr.
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Publication number: 20220302925Abstract: One or more systems and/or methods for implementing an analog-to-digital converter system with a floating digital channel configuration are provided. An analog input component is configured to receive measured analog signals, and output analog signals, corresponding to the measured analog signals, to an analog channel coupled to the analog input component. The analog channel is coupled to a switching component connected to a first digital channel and a second digital channel. The analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel.Type: ApplicationFiled: April 28, 2021Publication date: September 22, 2022Applicant: Cypress Semiconductor CorporationInventors: Eric N. Mann, Erhan Hancioglu, Eashwar Thiagarajan, Harold Kutz, Amsby D Richardson, JR.
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Patent number: 11437961Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.Type: GrantFiled: June 26, 2020Date of Patent: September 6, 2022Assignee: Cypress Semiconductor CorporationInventors: Erhan Hancioglu, Eashwar Thiagarajan, Eric Mann, Harold Kutz, Vaibhav Ramamoorthy, Rajiv Singh, Amsby Richardson, Jr.
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Patent number: 11251805Abstract: A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.Type: GrantFiled: October 16, 2020Date of Patent: February 15, 2022Assignee: Cypress Semiconductor CorporationInventors: Eashwar Thiagarajan, Erhan Hancioglu, Eric N. Mann, Harold Kutz, Amsby D Richardson, Jr., Rajiv Singh
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Publication number: 20210408986Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Applicant: Cypress Semiconductor CorporationInventors: Erhan Hancioglu, Eashwar Thiagarajan, Eric Mann, Harold Kutz, Vaibhav Ramamoorthy, Rajiv Singh, Amsby Richardson, JR.
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Publication number: 20210409034Abstract: A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.Type: ApplicationFiled: October 16, 2020Publication date: December 30, 2021Applicant: Cypress Semiconductor CorporationInventors: Eashwar Thiagarajan, Erhan Hancioglu, Eric N. Mann, Harold Kutz, Amsby D. Richardson, JR., Rajiv Singh
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Patent number: 11105851Abstract: A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.Type: GrantFiled: March 17, 2020Date of Patent: August 31, 2021Assignee: Cypress Semiconductor CorporationInventors: Harold Kutz, Timothy John Williams, Bert Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
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Patent number: 10848170Abstract: A method can include, amplifying an analog input signal to generate an amplified analog signal; modulating the amplified analog signal into a digital data stream; filtering the digital data stream with a first digital filter to generate a first filtered data stream, and selectively changing a gain of the amplifier in response to the first filtered data stream. While the digital data stream is filtered with the first digital filter, the digital data stream is filtered with a second digital filter to generate a second filtered data stream. An output digital value corresponding to the analog input signal in response to the second filtered data stream. Corresponding systems and devices are also disclosed.Type: GrantFiled: June 26, 2020Date of Patent: November 24, 2020Assignee: Cypress Semiconductor CorporationInventors: Eashwar Thiagarajan, Erhan Hancioglu, Eric Mann, Harold Kutz, Amsby Richardson, Jr., Rajiv Singh
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Publication number: 20200300910Abstract: A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.Type: ApplicationFiled: March 17, 2020Publication date: September 24, 2020Applicant: Cypress Semiconductor CorporationInventors: Harold Kutz, Timothy John Williams, Bert Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
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Patent number: 10762019Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.Type: GrantFiled: July 11, 2017Date of Patent: September 1, 2020Assignee: Cypress Semiconductor CorporationInventors: Timothy John Williams, David G. Wright, Harold M. Kutz, Eashwar Thiagarajan, Warren S. Snyder, Mark E Hastings
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Patent number: 10634722Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.Type: GrantFiled: May 23, 2019Date of Patent: April 28, 2020Assignee: Cypress Semiconductor CorporationInventors: Harold Kutz, Timothy John Williams, Bert Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
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Publication number: 20200083889Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.Type: ApplicationFiled: March 29, 2019Publication date: March 12, 2020Applicant: Cypress Semiconductor CorporationInventors: Eashwar Thiagarajan, Andrew Page, Harold Kutz, Kendall Castor-Perry, Rajiv Singh, Erhan Hancioglu, Bert Sullam
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Publication number: 20190227818Abstract: A device includes an analog block array, a first analog bus segment coupled to the analog block array, a second analog bus segment coupled to the analog block array, and a third analog bus segment coupled to the analog block array. The device also includes a first I/O pin selectively couplable to the first analog bus segment, a second I/O pin selectively couplable to the second analog bus segment, and a third I/O pin selectively couplable to the third analog bus segment. A first switch is configured to selectively propagate a first analog signal on the first analog bus segment to the second analog bus segment, and a second switch is configured to selectively propagate a second analog signal on the first analog bus segment to the third analog bus segment. In a first mode of operation, the first and second switches are open. In a second mode of operation, the first switch is closed. In a third mode of operation, the second switch is closed.Type: ApplicationFiled: April 4, 2019Publication date: July 25, 2019Applicant: Cypress Semiconductor CorporationInventors: Harold M. Kutz, Warren S. Snyder, Timothy John Williams, Eashwar Thiagarajan
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Patent number: 10345377Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.Type: GrantFiled: April 3, 2018Date of Patent: July 9, 2019Assignee: Cypress Semiconductor CorporationInventors: Harold M. Kutz, Timothy John Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E. Hastings, Dennis R. Seguine
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Publication number: 20180292454Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.Type: ApplicationFiled: April 3, 2018Publication date: October 11, 2018Applicant: Cypress Semiconductor CorporationInventors: Harold M. Kutz, Timothy John Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
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Patent number: 10033403Abstract: An integrated circuit device can include at least one input; at least one output configured to provide a multi-bit output value; at least one input; at least one output configured to provide a multi-bit output value; a plurality of configurable digital filter circuits; and switch circuits coupled to the at least one input and to the at least one output, the switch circuits configurable to connect same digital filter circuits as a single processing path or separate processing paths.Type: GrantFiled: June 11, 2015Date of Patent: July 24, 2018Assignee: Cypress Semiconductor CorporationInventors: Eashwar Thiagarajan, Jean-Paul Vanitegem, Harold M. Kutz, Anasuya Pai Maroor, Kendall V. Castor-Perry