Patents by Inventor Eberhard Amann
Eberhard Amann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9229730Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.Type: GrantFiled: December 17, 2014Date of Patent: January 5, 2016Assignee: International Business Machines CorporationInventors: Eberhard Amann, Frank Haverkamp, Thomas Huth, Jan Kunigk
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Publication number: 20150106613Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.Type: ApplicationFiled: December 17, 2014Publication date: April 16, 2015Inventors: Eberhard Amann, Frank Haverkamp, Thomas Huth, Jan Kunigk
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Patent number: 8996770Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.Type: GrantFiled: August 23, 2012Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Eberhard Amann, Frank Haverkamp, Jan Kunigk, Thomas Huth
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Patent number: 8954721Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.Type: GrantFiled: December 8, 2011Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: Eberhard Amann, Frank Haverkamp, Thomas Huth, Jan Kunigk
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Patent number: 8954639Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.Type: GrantFiled: September 6, 2011Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: Eberhard Amann, Frank Haverkamp, Jan Kunigk, Thomas Huth
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Publication number: 20130151829Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.Type: ApplicationFiled: December 8, 2011Publication date: June 13, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eberhard Amann, Frank Haverkamp, Thomas Huth, Jan Kunigk
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Publication number: 20130060986Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.Type: ApplicationFiled: September 6, 2011Publication date: March 7, 2013Applicant: International Business Machines CorporationInventors: Eberhard Amann, Frank Haverkamp, Jan Kunigk, Thomas Huth
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Publication number: 20130060978Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.Type: ApplicationFiled: August 23, 2012Publication date: March 7, 2013Applicant: International Business Machines CorporationInventors: Eberhard Amann, Frank Haverkamp, Jan Kunigk, Thomas Huth
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Patent number: 6625176Abstract: A method is provided to adjust time delays and sequence ordering of data channels in synchronous clocked bus systems. In particular, the invention relates to a method to re-synchronize data in respective channels which have a relative delay to each other caused by different path lengths, etc., on the way from sender to receiver. Still more specifically, the invention relates to an apparatus used to eliminate those delays in order to make data usable again on the receiver side. The method can be carried out using standard microprocessors without the need for special hardware implementations. Thus the use of costly and performance intensive ASICs and signal processors can be avoided.Type: GrantFiled: April 29, 1999Date of Patent: September 23, 2003Assignee: International Business Machines CorporationInventors: Eberhard Amann, Helga Hermann, Juergen Saalmueller
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Patent number: 6560201Abstract: Method and apparatus are provided for re-synchronizing a group of B channels in an ISDN network using the BONDING Mode 1 specification. Re-synchronization is achieved without the need to first disconnect the affected group of B channels from the network. Thus, the reliability of the bonded channels is improved while maintaining a simpler architecture than those associated with BONDING Modes 2 and 3. The solution offers improved channel reliability, improved network performance and reduced network load when channel re-synchronization becomes necessary.Type: GrantFiled: April 29, 1999Date of Patent: May 6, 2003Assignee: International Business Machines CorporationInventors: Eberhard Amann, Helga Hermann, Juergen Saalmueller