Abstract: Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: A method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices.

Abstract: Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices.

Abstract: A computer system for simulating performance of transmission lines, such as on-chip interconnects. The simulation uses direct extraction of poles, in contrast to conventional methods using poles obtained by a truncated transfer function. Using the directly extracted poles, far end response characteristic(s) can be determined to thereby aid in design of circuits using transmission lines. The far end response characteristic(s) that may be determined based on the directly extracted poles include, but are not necessarily limited to, frequency dependent effects, step response, ramp response, delay, 50% delay, rise time, 10% to 90% rise time, overshoot and normalized overshoot. A CAE tool designer and/or CAE tool user may decide how many pole pairs to directly extract to achieve a desired balance between computation resources required and resulting precision in the determination of far end response characteristic(s).

Abstract: CMOS voltage interface circuits have low power consumption, and minimal delays and power dissipation for the driving strength of the output. The circuits use a interface block which is operative upon the applied input signal, depending upon its state and timing, to generate the output at a specified voltage level which may be different from the level of the applied input.

Abstract: Circuit useful as current mirror and/or current divider has a circuit topology containing mirror and reference transistor pairs, respectively provided by MOS P and N type transistors for the up and down mirrors. The mirror transistor in each pair is followed by a buffer transistor which provides the current output. The topology obtains equal input and output currents through the DC biasing of the reference and mirror transistors by providing equality of the D to S and G to S voltages operative in both the reference and mirror transistors of both mirrors. The topology provides matched performance for the up and down current mirrors with very high mirroring accuracy, design insensitive up and down mirrored current, excellent operation over a wide power supply range, temperature insensitive precision, and the possibility of conveniently obtaining a wide range of current divisions.

Abstract: CMOS buffer circuits are provided having multiple stages of driving transistors defining a fast "1" data path and a fast "0" data path for transmitting data signals from the input to output of the buffer. Each stage before the last stage in each of the data paths has at least one nulling transistor coupled to the driving transistor of the stage. Separate from the data paths, the nulling transistors of each data path are operated to synchronously null the driving transistors of the data path to prepare such driving transistors for the next fast transition in the input data signal. Another nulling transistor may be also coupled to the driving transistor of each stage before the last stage of each data path which prevents the data path from floating when the data path is not transmitting a transition of the input signal to output of the buffer.