Abstract: Peak-to-average ratio reduction is achieved by detecting peaks in an original analog signal that exceed a given threshold. Segments of the original analog signal containing such peaks are treated (e.g., by attenuation) and a composite analog signal is assembled that includes treated and untreated segments of the original analog signal. The composite analog signal is processed to perform analog-to-digital conversion to generate a composite digital signal. Segments of the composite digital signal corresponding to the treated segments of the original analog signal are reverse-treated or otherwise treated again to undo treatment of the segments of the original analog signal. A final output digital signal is generated that corresponds to the original analog signal in digital form.

Abstract: Driver circuits for switched-capacitor circuits are implemented using a variety of methods and devices. According to one such circuit, a switched-capacitor driver circuit is implemented for producing an output signal by driving a capacitive output load in response to step input signals. The driver circuit includes output circuitry that drives the capacitive output load toward a steady-state mode responsive to one of the step input signals and control circuitry that, before realizing the steady-state mode, inhibits the output circuitry from driving the capacitive output load to the steady-state mode.

Abstract: A current compensation circuit for use with a current mirror is disclosed. The current mirror circuit has a current path defined by a first current mirror stage driving a second current mirror stage, the second current mirror stage is coupled to a supply voltage source. The current compensation circuit comprises an impedance divider coupled to the supply voltage and an output node. The impedance divider operates to generate a compensation signal at the node representative of voltage changes in the supply voltage source. The compensation circuit further includes a gain stage having an input coupled to the output node and a current output connected to the current path. The gain stage operates to generate a compensation current for application to the current path in response to the compensation signal.

Abstract: A current compensation circuit for use with a current mirror is disclosed. The current mirror circuit has a current path defined by a first current mirror stage driving a second current mirror stage, the second current mirror stage is coupled to a supply voltage source. The current compensation circuit comprises an impedance divider coupled to the supply voltage and an output node. The impedance divider operates to generate a compensation signal at the node representative of voltage changes in the supply voltage source. The compensation circuit further includes a gain stage having an input coupled to the output node and a current output connected to the current path. The gain stage operates to generate a compensation current for application to the current path in response to the compensation signal.

Abstract: An apparatus for providing a read signal at an output locus for access by an information processing device receives an input signal containing the information; the apparatus includes: (a) a read signal control unit receiving the input signal at a control unit input locus; the control unit is coupled with the output locus and controls the read signal; (b) a plurality of switches; and (c) a plurality of bias arrays coupled with the switches. A first bias array set cooperates with the plurality of switches in a first orientation to couple the first bias array set with the control unit to establish a first operational mode. A second bias array set cooperates with the plurality of switches in a second orientation to couple the second bias array set with the control unit to establish a second operational mode.

Abstract: An improved bias circuit for a disk drive head which reduces or eliminates transients while switching biasing. Embodiments of the invention are directed to eliminating transients while switching the bias of a MR head such as from current bias to voltage biasing. In an embodiment of the present invention, bias enable signals from a control circuit are inputs to delay circuits. The delay circuits provide a delay on the high-to-low transition, and essentially no delay on the low-to-high transition. The unsymmetrical delay ensures that the read head bias current will continue to be driven during the biasing transition to reduce voltage swings that could damage the head.

Abstract: The present invention relates to a method of enhancing a preamplifier read recovery in a hard disk drive system and comprises the steps of determining whether the hard disk drive system is transitioning from a non-read state to a read state and initiating a non-read state to a read state transition sequence when a transition from the non-read state to the read state is determined. The transition sequence is independent of a type of non-read state prior to the transitioning. After the non-read state to read state transition sequence is complete the read mode is initiated. In addition, the invention comprises a system for controlling a transition from a non-read state to a read state associated with a preamplifier in a hard disk drive system.

Abstract: A method and circuit for selectively timing amplifier stages of a multi-stage reader amplifier for a hard disk drive system. The reader amplifier includes a first stage, second stage and third stage coupled in series. The method includes the steps of powering the first stage, delaying the enabling of the second stage, and delaying the enabling of the third stage, in order to reduce excursions on the third stage output signal. The circuit includes a logic circuit for successively enabling the second and third amplifier stages.

Abstract: An apparatus for providing a read signal at an output locus for access by an information processing device receives an input signal containing the information; the apparatus includes: (a) a read signal control unit receiving the input signal at a control unit input locus; the control unit is coupled with the output locus and controls the read signal; (b) a plurality of switches; and (c) a plurality of bias arrays coupled with the switches. A first bias array set cooperates with the plurality of switches in a first orientation to couple the first bias array set with the control unit to establish a first operational mode. A second bias array set cooperates with the plurality of switches in a second orientation to couple the second bias array set with the control unit to establish a second operational mode.

Abstract: An adjustable impedance boosting circuit for a magneto-resistive head in a gain stage beyond the input gain stage. The boosting circuit compensates for a frequency pole of the head leads by introducing a zero in proportion to the resistance of the magneto-resistive element and with selectable circuit parameters to further adjust the pole compensation. The invention includes selectively adjusting the sensitivity of the pole compensation to changes in the resistance of the head, selectively adjusting the peak compensation, and adjusting the frequency of the compensating zero.

Abstract: A differential circuit to read differential data from a disk by a voltage bias includes a read circuit to read the differential data from the disk by maintaining the voltage bias by a first transistor and a second transistor, the first transistor being positioned in a first current path to maintain a first current and the second transistor being positioned in a second current path to maintain a second current. The first current is approximately equal to the second current.

Abstract: A circuit (80) and method (84) for protecting read heads (18) of a hard-disk drive system (100). Capacitor C1 is controllably coupled to a dummy head Rdummy during a Vbias mode, so that capacitor C1 has a low, predictable voltage upon returning to Ibias mode, protecting the read heads (18) from damage. The circuit (80) includes logic (82) and algorithm (84) determining when to couple the capacitor C1 to the dummy head Rdummy during a servo bank write (SBW) sequence.

Abstract: A preamplifier circuit for a hard disk drive system comprises a preamplifier circuit having a bias voltage circuit stage associated therewith. The preamplifier circuit further comprises a current bias boost recovery circuit operatively coupled to the bias voltage circuit stage which is configured to increase a rate of charging of a noise reduction capacitor associated with the bias voltage circuit stage. A head select boost recovery circuit is also operatively coupled to the bias voltage circuit and is configured to increase a rate of charging or discharging of a bias capacitor associated with the bias voltage circuit stage. Together the circuits allow for a concurrent head switch and current bias switch and avoids the problems associated with the prior art.

Abstract: A selectively adjustable impedance boosting circuit for a magneto-resistive head in a disk drive to compensate a frequency pole by introducing a zero in proportion to the resistance of the magneto-resistive element and with selectable circuit parameters to further adjust the pole compensation. The invention includes selectively adjusting the sensitivity of the pole compensation to changes in the resistance of the head, selectively adjusting the peak compensation, and adjusting the frequency of the compensating zero.

Abstract: An offset circuit to correct an offset between differential signals includes a read circuit to read the differential signals, a circuit to measure the offset of the differential signals, and a programmable trim circuit to compensate for the offset of said differential signals.

Abstract: A circuit to voltage bias a first head to access a disk includes a circuit to bias the head with said voltage, a feedback circuit to measure the voltage and generate a feedback signal to correct deviations in the voltage, and a switch circuit to switch the feedback circuit to a serial head while maintaining the feedback head or said first head.

Abstract: A differential circuit to read differential data from a disk by a voltage bias includes a read circuit to read the differential data from the disk by maintaining the voltage bias by a first transistor and a second transistor, the first transistor being positioned in a first current path to maintain a first current and the second transistor being positioned in a second current path to maintain a second current. The first current is approximately equal to the second current.

Abstract: An integrated circuit having a pinout configuration, having a first configuration of pins and a circuit to change the integrated circuit to a second configuration of pins.

Abstract: A magneto-resistive head preamplifier structure has a difference amplifier with cross-coupled transistors configured to cancel the adverse effects on preamplified output signals due to parasitic capacitance associated with the difference amplifier transistors. The cross-coupled transistors extend the useable bandwidth of the preamplifier by substantially reducing internally generated thermal noise.

Abstract: An integrated circuit having a pinout configuration, having a first configuration of pins and a circuit to change the integrated circuit to a second configuration of pins.