Abstract: A surge protection device for providing bidirectional detections of one or more surge events. The device has low dynamic resistance during a surge protection mode, and it conducts ultra-low leakage current outside of the surge protection mode. In one implementation, the device includes first and second power transistors, a sensing circuit, and a driver circuit. The first power transistor includes a first source terminal that is coupled to the substrate, and the second power transistor includes a second source terminal that is coupled to the substrate. The sensing circuit is configured to detect a voltage of the first pin relative to the second pin and generate a sense signal when the voltage exceeds a threshold. The driver circuit is configured to generate a driver signal based on the sense signal and output the driver signal to at least one of the first or second gate terminal.

Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.

Abstract: A surge protection device for providing bidirectional detections of one or more surge events. The device has low dynamic resistance during a surge protection mode, and it conducts ultra-low leakage current outside of the surge protection mode. In one implementation, the device includes first and second power transistors, a sensing circuit, and a driver circuit. The first power transistor includes a first source terminal that is coupled to the substrate, and the second power transistor includes a second source terminal that is coupled to the substrate. The sensing circuit is configured to detect a voltage of the first pin relative to the second pin and generate a sense signal when the voltage exceeds a threshold. The driver circuit is configured to generate a driver signal based on the sense signal and output the driver signal to at least one of the first or second gate terminal.

Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.

Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.

Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.