Patents by Inventor Eddy Chiang

Eddy Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6458706
    Abstract: A new method is provided to treat contact holes after hole formation has been completed. A layer of non-conformal dielectric is deposited over the surface in which the contact hole has been formed thereby including the sidewalls and bottom of the contact hole. The non-conformal dielectric will be unevenly deposited on The sidewalls and bottom of the contact hole. This results in a relatively light deposition of non-conformal dielectric along the lower portions of the sidewalls and on the bottom of the contact hole with a heavier coating of non-conformal dielectric being deposited along the upper reaches of the contact hole. The objective of the invention is to prevent the enlargement of the hole diameter during subsequent processing steps. The non-conformal dielectric can be removed from the bottom using a wet etch.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: October 1, 2002
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Eddy Chiang, Erik S. Jeng, I-Ping Lee, Kuei-Chuen Ho
  • Patent number: 6376384
    Abstract: A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and oxygen.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: April 23, 2002
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tzu-Shih Yen, Erik S. Jeng, I-Ping Lee, Eddy Chiang
  • Patent number: 6306759
    Abstract: A method for forming self-aligned contact (SAC) is disclosed to improve device reliability. The method includes forming a dielectric liner over the contact opening before the contact plug is filled in. Optional contact implantation before and after the liner formation can be added to enhance the doping profile of the device.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: October 23, 2001
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tzu-Shih Yen, Erik S. Jeng, Hsiao-Chin Tuan, Chun-Yao Chen, Eddy Chiang, Wen-Shiang Liao