Patents by Inventor Eddy Pramono
Eddy Pramono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9582626Abstract: Accurate timing analysis during STA is performed using detailed waveform information in addition to the traditional slew information. A waveform memory system efficiently stores the detailed waveforms that are used in, calculated during, and propagated throughout timing analysis for a circuit design. During the STA process, for multiple modeled stages of circuit design, a waveform including information detailing the form of the waveform is compressed, stored in, decompressed, and retrieved from a memory system. The memory system provides for storage efficiencies including long-term and short-term storage areas, multi-level storage, and separate storage for each view evaluated during the STA.Type: GrantFiled: November 20, 2014Date of Patent: February 28, 2017Assignee: Cadence Design Systems, Inc.Inventors: Igor Keller, Eddy Pramono, Jijun Chen, Nikolay Rubanov
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Patent number: 8694934Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.Type: GrantFiled: May 21, 2012Date of Patent: April 8, 2014Assignee: Cadence Design Systems, Inc.Inventors: Eddy Pramono, Yong Zhan, Vinod Kariat
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Patent number: 8566760Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.Type: GrantFiled: May 21, 2012Date of Patent: October 22, 2013Assignee: Cadence Design Systems, Inc.Inventors: Eddy Pramono, Yong Zhan, Vinod Kariat
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Patent number: 8543952Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.Type: GrantFiled: November 4, 2011Date of Patent: September 24, 2013Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Patent number: 8504958Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.Type: GrantFiled: October 7, 2011Date of Patent: August 6, 2013Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Publication number: 20120304137Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.Type: ApplicationFiled: May 21, 2012Publication date: November 29, 2012Inventors: Eddy Pramono, Yong Zhan, Vinod Kariat
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Publication number: 20120297357Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.Type: ApplicationFiled: May 21, 2012Publication date: November 22, 2012Inventors: Eddy Pramono, Yong Zhan, Vinod Kariat
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Publication number: 20120210285Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.Type: ApplicationFiled: November 4, 2011Publication date: August 16, 2012Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Patent number: 8201113Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distribution show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.Type: GrantFiled: July 25, 2008Date of Patent: June 12, 2012Assignee: Cadence Design Systems, Inc.Inventors: Eddy Pramono, Yong Zhan, Vinod Kariat
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Publication number: 20120102449Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.Type: ApplicationFiled: October 7, 2011Publication date: April 26, 2012Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Patent number: 8104007Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.Type: GrantFiled: June 24, 2008Date of Patent: January 24, 2012Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Patent number: 8103996Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.Type: GrantFiled: April 1, 2009Date of Patent: January 24, 2012Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Patent number: 8104006Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express the temperature dependence of the power dissipation for several circuit modules. In some embodiments, the power dissipation equations express a non-linear relationship between power dissipation and temperature. The method defines a heat flow equation based on the specified power dissipation equations. The method then solves the heat flow equation to identify a temperature distribution for the design layout.Type: GrantFiled: January 31, 2008Date of Patent: January 24, 2012Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Igor Keller, Eddy Pramono
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Publication number: 20100023903Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distribution show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.Type: ApplicationFiled: July 25, 2008Publication date: January 28, 2010Inventors: Eddy Pramono, Yong Zhan, Vinod Kariat
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Publication number: 20090319965Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.Type: ApplicationFiled: April 1, 2009Publication date: December 24, 2009Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Publication number: 20090319964Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.Type: ApplicationFiled: June 24, 2008Publication date: December 24, 2009Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Publication number: 20090199140Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express the temperature dependence of the power dissipation for several circuit modules. In some embodiments, the power dissipation equations express a non-linear relationship between power dissipation and temperature. The method defines a heat flow equation based on the specified power dissipation equations. The method then solves the heat flow equation to identify a temperature distribution for the design layout.Type: ApplicationFiled: January 31, 2008Publication date: August 6, 2009Inventors: Vinod Kariat, Igor Keller, Eddy Pramono
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Patent number: 7024644Abstract: Diffusion effects during an IC fabrication process cause actual dimensions of adjacent conductors in an IC to vary from nominal dimensions specified by data defining the IC layout. A computer-aided design tool processes the layout data to generate a separate database for each layer of the IC, including a separate table corresponding to each grid line of that layer. Each table includes a separate table entry corresponding to each conductor to reside along the table's corresponding grid line, each table entry indicating nominal dimensions and position of its corresponding conductor. The tool sorts grid line tables within each layer's database in an order in which their corresponding grid lines are arranged on that layer, and sorts entries in each table in an order in which their corresponding conductors are to appear along the table's corresponding grid line.Type: GrantFiled: May 8, 2003Date of Patent: April 4, 2006Assignee: Cadence Design Systems, Inc.Inventor: Eddy Pramono
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Patent number: 6925619Abstract: An RC extraction tool estimates capacitances of conductors residing along parallel grid lines on each of a set vertically stacked layers of insulating material of an IC based on data contained in a IC layout file describing positions of structures forming the IC. The tool initially processes the layout file to generate a separate database for each layer. Each database includes a separate table for each grid line on its corresponding layer, and each table includes a separate entry for each conductor residing along that grid line containing data indicating dimensions and a position of its corresponding conductor along that grid line. The tool processes the databases for each layer in ascending order to estimate capacitances between conductors on that layer and to generate set of data structures mapping the amount of conductor surface area on that layer to areas of layers above that layer, and to areas of layers below that layer in which conductors reside.Type: GrantFiled: May 21, 2003Date of Patent: August 2, 2005Assignee: Cadence Design Systems, Inc.Inventors: Chin-Chi Teng, Eddy Pramono
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Publication number: 20040237058Abstract: An RC extraction tool estimates capacitances of conductors residing along parallel grid lines on each of a set vertically stacked layers of insulating material of an IC based on data contained in a IC layout file describing positions of structures forming the IC. The tool initially processes the layout file to generate a separate database for each layer. Each database includes a separate table for each grid line on its corresponding layer, and each table includes a separate entry for each conductor residing along that grid line containing data indicating dimensions and a position of its corresponding conductor along that grid line. The tool processes the databases for each layer in ascending order to estimate capacitances between conductors on that layer and to generate set of data structures mapping the amount of conductor surface area on that layer to areas of layers above that layer, and to areas of layers below that layer in which conductors reside.Type: ApplicationFiled: May 21, 2003Publication date: November 25, 2004Inventors: Chin-Chi Teng, Eddy Pramono