Patents by Inventor Edgar Borrayo
Edgar Borrayo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10223298Abstract: Embodiments of the invention include a machine-readable medium having stored thereon instructions, which if performed by a machine causes the machine to perform a method that includes assigning an urgency of requests based on a priority level for incoming requests and associated entries in at least one priority queue, assigning an urgency delta for anti-starvation that indicates urgency promotion to prevent starvation for the incoming requests in the at least one priority queue, determining conflict information including whether an incoming request is dependent on any request already present in the at least one queue, determining all contending requests within the at least one priority queue during a cycle, and sending a selected contending request to a memory controller for accessing memory.Type: GrantFiled: December 12, 2016Date of Patent: March 5, 2019Assignee: INTEL CORPORATIONInventors: Siddhartha Chhabra, Men Long, Carlos Cornelas Ornelas, Edgar Borrayo, Alpa T. Narendra Trivedi
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Publication number: 20180165229Abstract: Embodiments of the invention include a machine-readable medium having stored thereon instructions, which if performed by a machine causes the machine to perform a method that includes assigning an urgency of requests based on a priority level for incoming requests and associated entries in at least one priority queue, assigning an urgency delta for anti-starvation that indicates urgency promotion to prevent starvation for the incoming requests in the at least one priority queue, determining conflict information including whether an incoming request is dependent on any request already present in the at least one queue, determining all contending requests within the at least one priority queue during a cycle, and sending a selected contending request to a memory controller for accessing memory.Type: ApplicationFiled: December 12, 2016Publication date: June 14, 2018Inventors: Siddhartha Chhabra, Men Long, Carlos Cornelas Ornelas, Edgar Borrayo, Alpa T. Narendra Trivedi
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Patent number: 9980168Abstract: This application discusses apparatus and methods of saving power using a quadrature receiver by enabling a single string reception mode of the quadrature receiver. In an example, a receiver for receiving communication information can include an analog front end configured to receive a modulated, information-carrying radio frequency signal at a first frequency band and to provide a digital representation of the modulated, information-carrying radio frequency signal at a second frequency band, a digital front end configured to receive the digital representation at the second frequency and to provide the communication information, for example, to a baseband processor. In a first processing mode of the receiver, the analog front end can provide either one of in-phase symbol information of the modulated, information-carrying radio frequency signal or quadrature symbol information of the modulated, information-carrying radio frequency signal at the second frequency band.Type: GrantFiled: June 25, 2015Date of Patent: May 22, 2018Assignee: Intel CorporationInventors: David Arditti Ilitzky, Thomas A. Tetzlaff, Edgar Borrayo, Stefano Pellerano
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Patent number: 9910793Abstract: Memory encryption engine (MEE) integration technologies are described. A MEE system may include a MEE interface and a MEE core. The MEE interface may receive a data from an arbiter, where the data is selected by the arbiter from data at memory link queues. The MEE interface may adjust a timing rate to send the data to match a timing of a MEE core. The MEE core may be coupled to the MEE interface and may receive the data from the MEE interface.Type: GrantFiled: November 22, 2016Date of Patent: March 6, 2018Assignee: Intel CorporationInventors: Siddhartha Chhabra, Uday R. Savagaonkar, Men Long, Edgar Borrayo, Alpa T. Narendra Trivedi, Carlos Ornelas
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Publication number: 20170075822Abstract: Memory encryption engine (MEE) integration technologies are described. A MEE system may include a MEE interface and a MEE core. The MEE interface may receive a data from an arbiter, where the data is selected by the arbiter from data at memory link queues. The MEE interface may adjust a timing rate to send the data to match a timing of a MEE core. The MEE core may be coupled to the MEE interface and may receive the data from the MEE interface.Type: ApplicationFiled: November 22, 2016Publication date: March 16, 2017Inventors: Siddhartha Chhabra, Uday R. Savagaonkar, Men Long, Edgar Borrayo, Alpa T. Narendra Trivedi, Carlos Ornelas
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Publication number: 20160381643Abstract: This application discusses apparatus and methods of saving power using a quadrature receiver by enabling a single string reception mode of the quadrature receiver. In an example, a receiver for receiving communication information can include an analog front end configured to receive a modulated, information-carrying radio frequency signal at a first frequency band and to provide a digital representation of the modulated, information-carrying radio frequency signal at a second frequency band, a digital front end configured to receive the digital representation at the second frequency and to provide the communication information, for example, to a baseband processor. In a first processing mode of the receiver, the analog front end can provide either one of in-phase symbol information of the modulated, information-carrying radio frequency signal or quadrature symbol information of the modulated, information-carrying radio frequency signal at the second frequency band.Type: ApplicationFiled: June 25, 2015Publication date: December 29, 2016Inventors: David Arditti Ilitzky, Thomas A. Tetzlaff, Edgar Borrayo, Stefano Pellerano
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Patent number: 9524249Abstract: Memory encryption engine (MEE) integration technologies are described. A processor can include a processor core and an arbiter of a MEE system coupled to the processor core. The arbiter can receive a first contending request from a first queue and a second contending request from a second queue. The arbiter can further select the first queue to communicate the first message to an MEE of the MEE system or the second queue to communicate the second message to the MEE in view of arbitration criteria. The arbiter can further communicate the selected first message or the selected second message to the MEE.Type: GrantFiled: December 23, 2014Date of Patent: December 20, 2016Assignee: Intel CorporationInventors: Siddhartha Chhabra, Uday R. Savagaonkar, Men Long, Edgar Borrayo, Alpa T. Narendra Trivedi, Carlos Ornelas
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Patent number: 9442864Abstract: A processor is described that includes one or more processing cores. The processor includes a memory controller to interface with a system memory having a protected region and a non protected region. The processor includes a protection engine to protect against active and passive attacks. The processor includes an encryption/decryption engine to protect against passive attacks. The protection engine includes bridge circuitry coupled between the memory controller and the one or more processing cores. The bridge circuitry is also coupled to the protection engine and the encryption/decryption engine. The bridge circuitry is to route first requests directed to the protected region to the protection engine and to route second requests directed to the non protected region to the encryption/decryption engine.Type: GrantFiled: December 27, 2013Date of Patent: September 13, 2016Assignee: Intel CorporationInventors: Uday R. Savagaonkar, Siddhartha Chhabra, Men Long, Alpa T. Narendra Trivedi, Carlos Ornelas, Edgar Borrayo, Ramadass Nagarajan, Stanley S. Kulick
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Publication number: 20160179702Abstract: Memory encryption engine (MEE) integration technologies are described. A processor can include a processor core and an arbiter of a MEE system coupled to the processor core. The arbiter can receive a first contending request from a first queue and a second contending request from a second queue. The arbiter can further select the first queue to communicate the first message to an MEE of the MEE system or the second queue to communicate the second message to the MEE in view of arbitration criteria. The arbiter can further communicate the selected first message or the selected second message to the MEE.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: Siddhartha Chhabra, Uday R. Savagaonkar, Men Long, Edgar Borrayo, Alpa T. Narendra Trivedi, Carlos Ornelas
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Patent number: 9276704Abstract: A wireless device, and corresponding method, having a receiver configured to receive a signal having in-phase and quadrature components; a non-linear filter demodulator configured to translate noncoherently the in-phase and quadrature components into a phase domain signal; a coherence acquisition unit configured to estimate and correct at least one coherence parameter based on the in-phase and quadrature components and the phase domain signal; and a detector configured to detect information in the phase domain signal.Type: GrantFiled: December 15, 2014Date of Patent: March 1, 2016Assignee: Intel CorporationInventors: David Arditti Ilitzky, Edgar Borrayo Sandoval, Arturo Veloz, Rocio Hernandez Fabian
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Publication number: 20150186295Abstract: A processor is described that includes one or more processing cores. The processor includes a memory controller to interface with a system memory having a protected region and a non protected region. The processor includes a protection engine to protect against active and passive attacks. The processor includes an encryption/decryption engine to protect against passive attacks. The protection engine includes bridge circuitry coupled between the memory controller and the one or more processing cores. The bridge circuitry is also coupled to the protection engine and the encryption/decryption engine. The bridge circuitry is to route first requests directed to the protected region to the protection engine and to route second requests directed to the non protected region to the encryption/decryption engine.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Inventors: Uday R. Savagaonkar, Siddhartha Chhabra, Men Long, Alpa T. Narendra Trivedi, Carlos Cornelas Omelas, Edgar Borrayo, Ramadass Nagarajan, Stanley Steve Kulick