Abstract: A phased-locked loop phase detector for digital input signals in which digital summed value for a particular number of bits is equal to zero. Sampled and digitized data comprising a delay stage for delaying the data signal by a one or more sampling clock period is supplied to the phase detector as an input signal. The delayed data signal and the undelayed data signal are then supplied to a subtraction stage. The difference between the two input values is formed in this subtraction stage. The processing stage assigns one of a plurality of possible values to the respective differential value. The full differential value range is subdivided in a number of sub-ranges corresponding to the plurality of possible values. All differential values in one sub-range are assigned the same output value. The output of the subtraction stage is supplied to a filter/control stage.

Abstract: Tape recorder having a group of write heads which are arranged like a matrix in rows and columns, with each write head assigned in one row line and in one column line, and having a driver circuit for passing current through the row and column lines. A write head magnetizes a magnetic tape permanently only when its associated row and column lines have currents applied to them causing magnetic fields that reinforce one another in the magnetic tape. A common row return line is provided to which all the row lines are connected and a common column return line is provided to which all the column lines are connected.

Abstract: A head drum for a magnetic tape apparatus includes a stationary lower cylinder and a rotating upper cylinder on which at least one write/read head is securely arranged and interacts with a magnetic tape with an exchange of electromagnetic signals. Also provided are at least one amplifier which rotates together with an upper cylinder and amplifies the signals coming from the write/read head, and a rotating transformer for transferring electrical signals between the stationary lower cylinder and the rotating upper cylinder. Storage means for electrical energy arranged on the rotating upper cylinder is capable of supplying electrical power to all the electronic components rotating together with the upper cylinder. A controller is securely arranged on the rotating upper cylinder for monitoring the charge state of the storage means and controlling the duration of the energy transfer as a function of the charge state.

Abstract: A neural network is provided for equalizing distorted data signals. The data signal to be equalized is coupled via time-delay elements to a group of networks for weighting. The output signals of the networks for weighting are coupled to the input terminals of a plurality of neurons whose outputs are coupled, via a respective amplifier, to input terminals of a further neuron having an output terminals where the equalized data signal can be tapped.

Abstract: A method of controlling track following in a recorder which uses recording in oblique tracks of a magnetic tape without inactive areas between the tracks and wherein data gaps occur in the useful data sequence due to the change of tracks includes the step of filling the time period containing the data gaps with a predetermined sequence of cyclical modifications of code words representing amplitude and degree increments of a symmetrical train of oscillations. A sequence of code words is used to produce incremental portions of the train of symmetrical oscillations whereby a number of incremental portions forms a complete train of symmetrical oscillations. The code words are modified in synchronism with the clock rate at which the useful data of the recorder are clocked.

Abstract: A method and apparatus for setting the parameters of an equalizer. Equalizers are used for equalizing distorted signals. However, optimum equalization is only achieved when the parameters of the equalizer are optimally set. To set the parameters of an equalizer optimally, the output signal of the equalizer is rectified in a full-wave rectifier. The output signal of the latter is integrated in an integrator. The parameters of the equalizer are set by a microprocessor according to an algorithm. In one embodiment, when the integration time is predetermined, the parameters of the equalizer is changed until the level of the integrated signal becomes a maximum. In another embodiment, when the maximum level of the integrated signal is predetermined, the parameters of the equalizer are changed until the integration time becomes a minimum.