Abstract: An omni-directional triband antenna operates without ground radials with gain commensurate with a half wavelength vertical on each band. The triband antenna includes a dual-band twinlead J-pole providing half wavelength radiators for UHF and VHF, and an impedance transformer defining feedpoints to which a length Lc of coaxial cable is attached. The Lc lower end is the triband antenna connector port. Intermediate band radiators are first and second wire elements that collectively are a half-wavelength at the intermediate band. The first element is wound helically about the impedance transformer, with upper end floating and lower end connected to a first feedpoint. The second element is wound helically about the Lc upper portion of coaxial cable, with upper end connected to the remaining feedpoint, and lower end of the element floating. The helical windings radiate vertically and there is no cross-interference between antenna radiation in any of the three bands.

Abstract: An omni-directional antenna operable absent ground radials and providing at least 3 dB gain at a chosen wavelength relative to a dipole includes first and second like-oriented J-pole antennas and, coupled intermediate said J-pole antennas, a quarter-wavelength non-radiating delay line. Each J-pole antenna includes a half-wave radiating element, and a quarter-wavelength non-radiating section. The quarter-wavelength non-radiating delay line together with the quarter-wavelength non-radiation section of the second J-pole provide a half-wave non-radiating delay line. The result is that RF energy radiated by the first and second half-wave radiating elements are in proper phase, whereby gain is achieved. RF energy is coupled to the first J-pole antenna a distance ? above the zero impedance end of that antenna.

Abstract: An omni-directional antenna operable absent ground radials and providing at least 3 dB gain at a chosen wavelength relative to a dipole includes first and second like-oriented J-pole antennas and, coupled intermediate said J-pole antennas, a quarter-wavelength non-radiating delay line. Each J-pole antenna includes a half-wave radiating element, and a quarter-wavelength non-radiating section. The quarter-wavelength non-radiating delay line together with the quarter-wavelength non-radiation section of the second J-pole provide a half-wave non-radiating delay line. The result is that RF energy radiated by the first and second half-wave radiating elements are in proper phase, whereby gain is achieved. RF energy is coupled to the first J-pole antenna a distance ? above the zero impedance end of that antenna.

Abstract: An amplifier circuit uses capacitor as voltage sources so that the amplifier can achieve high precision gain without either ratioed capacitors or absolute value of capacitors or resistors. In one embodiment, the amplifier circuit includes two or more capacitors that are each charged up to the input voltage during the sample phase. Then, during the hold phase, the switching network operates to connect the two or more capacitors in series between the input and output terminals of an operational amplifier, thereby generating an output voltage being N times the input voltage, N being the total number of capacitors connected in series. The amplifier circuit of the present invention is capable of achieving very high precision gain with very high slew rate. In particular, the amplifier circuit achieves very accurate integer gain (1×, 2×, 3×, and so on). Fractional gains can also be obtained with the use of a ratioed capacitor.

Abstract: A current sensing method and circuit for reading out a sensor cell, and a sensing apparatus comprising an array of sensor cells arranged along column lines and a current sensing readout circuit coupled to each column line. The sensor cell is configured to assert a sensor current indicative of a sensed value. In operation, an input node of the readout circuit is coupled to the sensor cell, typically by a column line of a sensor array that includes the sensor cell. Preferably, to read out the sensor cell, the sensor current flows from the sensor cell to the input node and in response, the readout circuit charges a capacitor to a voltage indicative of the sensed value while clamping the input node at a potential that is at least substantially fixed.

Abstract: A reduced power analog-to-digital (A/D) converter is disclosed herein. Reference current to an op-amp used in an A/D converter is reduced during later conversion cycles in an A/D conversion process. The reference current to the op-amp can be reduced without sacrificing overall accuracy of the output of the analog-to-digital converter, even though reducing the current to the op-amp reduces the accuracy of the op-amp. This is possible because the op-amp only needs to operate at maximum accuracy during the first conversion cycle, and can operate at reduced levels of accuracy during later conversion cycles.

Abstract: A reduced power analog-to-digital (A/D) converter is disclosed herein. Reference current to an op-amp used in an A/D converter is reduced during later conversion cycles in an A/D conversion process. The reference current to the op-amp can be reduced without sacrificing overall accuracy of the output of the digital-to-analog converter, even though reducing the current to the op-amp reduces the accuracy of the op-amp. This is possible because the op-amp only needs to operate at maximum accuracy during the first conversion cycle, and can operate at reduced levels of accuracy during later conversion cycles.

Abstract: A unity gain analog signal amplifier for low voltage applications, with no DC level shifting so as to preserve dynamic range, a large bandwidth, a good driving capability for capacitive loads and a rail-to-rail output voltage range. A differential amplifier composed of matched MOSFETs is biased between current source and sink circuits. The current source is a current mirror which provides equal currents through the two branches of the differential amplifier, while the tail current is sunk by the current sink circuit. The analog input signal drives the gate terminal of one of the MOSFETs and the gate and drain terminals of the other MOSFET are connected together and provide the output signal. An additional current mirror branch driven by the current source and connected to the output terminal provides increased output current driving capacity and output voltage pull up.

Abstract: An operational amplifier in a bias voltage generator of a MOS current summing digital to analog converter corrects deviations in output current due to variations in drain to source voltages in current slaves caused by differing output resistances and supply voltages. Matching of MOS current sources uses an operational amplifier feedback circuit to create a controlled turn-on reference voltage used for biasing selected differential current paths so as to eliminate drain to source voltage variations in precisely ratioed current slave MOS transistors. One transistor of each differential current pair is enabled by a corresponding switch coupled to the turn-on reference voltage produced by the operational amplifier. In the preferred embodiment, the switches are CMOS transmission gates enabled by the binary digital input and its complement. Low voltage (3 volts) operation is achieved by having minimum number of stacked transistors between power supply voltages.

Abstract: An error correction technique for high-resolution analog-to-digital converters corrects for both component mismatch and circuit nonlinearity errors by utilizing look-up tables to store mismatch coefficients, which represent the errors introduced by component mismatch, as well as a series of offset and gain coefficients, which are utilized to form a piecewise-linear representation of the error introduced by circuit nonlinearities. The use of an independent gain and offset parameter for each segment of the piecewise-linear representation allows discontinuous functions to be accommodated. This leads to a more efficient implementation since it allows the error introduced by mismatch in the components representing the most significant bits to be included in the piecewise linear table, while separate lookup tables are used for the less significant bits.

Abstract: The comparison circuitry of a comparator is isolated from noise on the power supply and ground by utilizing transistors operating in the forward-active region to isolate the comparison circuitry. The comparison circuitry is further isolated from random noise spikes by utilizing delay and switching circuitry to control the duration of the comparison.

Abstract: A novel serial data communication interface architecture is provided having two modes of operation that are accessed through a chip select signal in combination with a successive approximation registers signal (SARS). Once the internal data conversion begins, the chip select signal may change to any signal state without interrupting the conversion process. Serial interface data output and SARS lines are tri-stated during conversion, while the chip select signal is high. This allows data input, data output, and SARS lines to serve other purposes during conversion. If chip select signal is high at the falling edge of SARS, converted data DO bits are then provided to an internal output register. However, DO data are not immediately routed to the output. Clocking of the output data does not resume until at the first transition to low of chip select signal after the falling edge of SARS.

Abstract: A CMOS constant gain operational amplifier (20) has two differential input circuits (22, 24), each having a current source (40, 40A) and a compensation circuit (45, 45A). Each compensation circuit (45, 45A) dynamically tracks the common mode input voltage relative to a respective supply voltage and generates a respective tracking voltage that is used to modulate the current source of the respective differential input circuit. By modulating the current sources in accordance with the common mode input voltage, the input circuits are maintained in their saturation mode of operation over almost the entire rail-to-rail voltage range of the operational amplifier. The amplification stage circuit (27) also includes a dynamic bias adjustment circuit (95) that adjusts the bias of pull-down transistors (88, 90, 92, 94) in the presence of high speed input signal transients so as to keep the pull-down transistors in the amplification stage circuit in their normal, saturation mode of operation.