Patents by Inventor Edmund B. Minshall

Edmund B. Minshall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10115608
    Abstract: A gas expansion module for use with semiconductor wafer loadlocks and other regulated-pressure components of semiconductor processing tools is provided. The gas expansion module may be barometrically isolated from the loadlock or other component and pumped down to a vacuum condition while the loadlock is performing operations at a higher pressure, such as ambient atmospheric conditions. After an initial pump-down of the loadlock is performed, the gas expansion module may be fluidly joined to the loadlock volume and the gases within each allowed to reach equilibrium. A further pump-down of the combined volume may be used to bring the loadlock pressure to a desired vacuum condition.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 30, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Edmund B. Minshall, Victor F. Morris, Ram Charan, Ronald A. Powell, Mukul Khosla
  • Publication number: 20160056032
    Abstract: Disclosed are methods of depositing films of material on semiconductor substrates. The methods may include flowing a film precursor into a processing chamber through a showerhead substantially maintained at a first temperature, and adsorbing the film precursor onto a substrate held on a substrate holder such that the precursor forms an adsorption-limited layer while the substrate holder is substantially maintained at a second temperature. The first temperature may be at least about 10° C. above the second temperature, or the first temperature may be at or below the second temperature. The methods may further include removing at least some unadsorbed film precursor from the volume surrounding the adsorbed film precursor, and thereafter reacting adsorbed film precursor to form a film layer. Also disclosed herein are apparatuses having a processing chamber, a substrate holder, a showerhead, and one or more controllers for operating the apparatus to employ the foregoing film deposition techniques.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 25, 2016
    Inventors: Chloe Baldasseroni, Adrien LaVoie, Hu Kang, Jun Qian, Purushottam Kumar, Andrew Duvall, Cody Barnett, Mohamed Sabri, Ramesh Chandrasekharan, Karl F. Leeser, David C. Smith, Seshasayee Varadarajan, Edmund B. Minshall
  • Publication number: 20130312835
    Abstract: A gas expansion module for use with semiconductor wafer loadlocks and other regulated-pressure components of semiconductor processing tools is provided. The gas expansion module may be barometrically isolated from the loadlock or other component and pumped down to a vacuum condition while the loadlock is performing operations at a higher pressure, such as ambient atmospheric conditions. After an initial pump-down of the loadlock is performed, the gas expansion module may be fluidly joined to the loadlock volume and the gases within each allowed to reach equilibrium. A further pump-down of the combined volume may be used to bring the loadlock pressure to a desired vacuum condition.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 28, 2013
    Inventors: Edmund B. Minshall, Victor F. Morris, Ram Charan, Ronald A. Powell, Mukul Khosla
  • Patent number: 8415261
    Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: April 9, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
  • Patent number: 8257781
    Abstract: A main reservoir holds cool reactant liquid. A reaction vessel for treating a substrate is connected to the main reservoir by a feed conduit. A heater is configured to heat reactant liquid in the feed conduit before the liquid enters the reaction vessel. Preferably, the heater is a microwave heater. A recycle conduit connects the reaction vessel with the main reservoir. Preferably, a recycle cooler cools reactant liquid in the recycle conduit before the liquid returns to the main reservoir. Preferably, an accumulation vessel is integrated in the feed conduit for accumulating, heating, conditioning and monitoring reactant liquid before it enters the reaction vessel. Preferably, a recycle accumulator vessel is integrated in the recycle conduit to accommodate reactant liquid as it empties out of the reaction vessel.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: September 4, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Eric G. Webb, Steven T. Mayer, David Mark Dinneen, Edmund B. Minshall, Christopher M. Bartlett, R. Marshall Stowell, Mark T. Winslow, Avishai Kepten, Jingbin Feng, Norman D. Kaplan, Richard K. Lyons, John B. Alexy
  • Patent number: 8043958
    Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: October 25, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
  • Patent number: 7811925
    Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: October 12, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
  • Patent number: 7690324
    Abstract: During fluid treatment of a substrate surface, a carrier/wafer assembly containing a substrate wafer closes the top of a microcell container. The carrier/wafer assembly and the container walls define a thin enclosed treatment volume that is filled with treating fluid, such as electroless plating solution. The thin fluid-treatment volume typically has a volume in a range of about from 100 ml to 500 ml. Preferably a container is heated and the treating fluid is pre-heated before being injected into the container. Preferably, the chemical composition, temperature, and other properties of fluid in the thin enclosed fluid-treatment volume are dynamically variable. A rinse shield and a rinse nozzle are located above the container. A carrier/wafer assembly in a rinse position substantially closes the top of the rinse shield.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: April 6, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Jingbin Feng, Steven T. Mayer, Daniel Mark Dinneen, Edmund B. Minshall, Christopher M. Bartlett, Eric G. Webb, R. Marshall Stowell, Mark T. Winslow, Avishai Kepten, Norman D. Kaplan, Richard K. Lyons, John B. Alexy
  • Patent number: 7605082
    Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: October 20, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
  • Patent number: 6815349
    Abstract: An apparatus for holding work pieces during electroless plating has certain improved features designed for use at relatively high temperatures (e.g., at least about 50 degrees C.). Cup and cone components of a “clamshell” apparatus that engage a work piece are made from dimensionally stable materials with relatively low coefficients of thermal expansion. Further, O-rings are removed from positions that come in contact with the work piece. This avoids the difficulty caused by O-rings sticking to work piece surfaces during high temperature processing. In place of the O-ring, a cantilever member is provided on the portion of the cone that contacts the work piece. Still further, the apparatus makes use of a heat transfer system for controlling the temperature of the work piece backside during plating.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: November 9, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Edmund B. Minshall, Kevin Biggs, R. Marshall Stowell, Wayne Fetters
  • Patent number: 6755954
    Abstract: An apparatus for electrochemical treatment of a substrate, in particular for electroplating an integrated circuit wafer. An apparatus preferably includes dynamically operable concentric anodes and dielectric shields in an electrochemical bath. Preferably, the bath height of an electrochemical bath, the substrate height, and the shape and positions of an insert shield and a diffuser shield are dynamically variable during electrochemical treatment operations. Step include varying anode current, bath height and substrate height, shield shape, and shield position.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: June 29, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Timothy Patrick Cleary, Michael John Janicki, Edmund B. Minshall, Thomas A. Ponnuswamy
  • Publication number: 20040065540
    Abstract: A treating head having a treating surface and a substrate treatment surface define a thin fluid gap that is filled with reactant liquid to form a thin liquid layer on the substrate for conducting a liquid chemical reaction treatment or other liquid treatment of the substrate. The thin liquid layer has a volume in a range of about from 50 ml to 500 ml. Preferably, the chemical composition, temperature, and other properties of liquid in the thin liquid layer are dynamically variable.
    Type: Application
    Filed: June 30, 2003
    Publication date: April 8, 2004
    Applicant: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan D. Reid, Timothy Patrick Cleary, Edmund B. Minshall, R. Marshall Stowell, Heung Lak Park
  • Publication number: 20020195352
    Abstract: An apparatus for electrochemical treatment of a substrate, in particular for electroplating an integrated circuit wafer. An apparatus preferably includes dynamically operable concentric anodes and dielectric shields in an electrochemical bath. Preferably, the bath height of an electrochemical bath, the substrate height, and the shape and positions of an insert shield and a diffuser shield are dynamically variable during electrochemical treatment operations. Step include varying anode current, bath height and substrate height, shield shape, and shield position.
    Type: Application
    Filed: April 4, 2002
    Publication date: December 26, 2002
    Inventors: Steven T. Mayer, Timothy Patrick Cleary, Michael John Janicki, Edmund B. Minshall, Thomas A. Ponnuswamy