Abstract: The present invention is realized by apparatus and methods for harvesting, storing, and generating energy by permanently placing a large rigid buoyant platform high in the earth's atmosphere, above clouds, moisture, dust, and wind. Long, strong and light tethers can connect the buoyant structure to the ground which can hold it in position against wind forces. Weights suspended from the buoyant platform with cables are raised and lowered by electric winches to store and release gravitational potential energy. High voltage transmission lines electrically connect the platform to the earth's surface. Electrical energy from the high voltage transmission lines or from photovoltaic arrays on the platform can be stored as gravitational potential energy and subsequently released as electricity from generators driven from the stored gravitational potential energy and used on the platform or transmitted via the high voltage transmission lines.

Abstract: The present invention is realized by apparatus and methods for harvesting, storing, and generating energy by permanently placing a large rigid buoyant platform high in the earth's atmosphere, above clouds, moisture, dust, and wind. Long, strong and light tethers can connect the buoyant structure to the ground which can hold it in position against wind forces. Weights suspended from the buoyant platform with cables are raised and lowered by electric winches to store and release gravitational potential energy. High voltage transmission lines electrically connect the platform to the earth's surface. Electrical energy from the high voltage transmission lines or from photovoltaic arrays on the platform can be stored as gravitational potential energy and subsequently released as electricity from generators driven from the stored gravitational potential energy and used on the platform or transmitted via the high voltage transmission lines.

Abstract: The present invention is realized by apparatus and methods for harvesting, storing, and generating energy by permanently placing a large rigid buoyant platform high in the earth's atmosphere, above clouds, moisture, dust, and wind. Long, strong and light tethers can connect the buoyant structure to the ground which can hold it in position against wind forces. Weights suspended from the buoyant platform with cables are raised and lowered by electric winches to store and release gravitational potential energy. High voltage transmission lines electrically connect the platform to the earth's surface. Electrical energy from the high voltage transmission lines or from photovoltaic arrays on the platform can be stored as gravitational potential energy and subsequently released as electricity from generators driven from the stored gravitational potential energy and used on the platform or transmitted via the high voltage transmission lines.

Abstract: The present invention is realized by apparatus and methods for harvesting, storing, and generating energy by permanently placing a large rigid buoyant platform high in the earth's atmosphere, above clouds, moisture, dust, and wind. Long, strong and light tethers can connect the buoyant structure to the ground which can hold it in position against wind forces. Weights suspended from the buoyant platform with cables are raised and lowered by electric winches to store and release gravitational potential energy. High voltage transmission lines electrically connect the platform to the earth's surface. Electrical energy from the high voltage transmission lines or from photovoltaic arrays on the platform can be stored as gravitational potential energy and subsequently released as electricity from generators driven from the stored gravitational potential energy and used on the platform or transmitted via the high voltage transmission lines.

Abstract: A cluster of computers including a plurality of processing nodes, a command network connecting to each of the processor nodes, and circuitry for addressing each of the processor nodes on the command network based on a position of the processor node on the command network.

Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: Apparatus and a method for booting each of a plurality of computer processor nodes in a cluster system to run the same cluster operating system.

Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set including the combination of code morphing software, and morph host processing hardware designed to execute instructions of a host instruction set, the combination of the code morphing software and the morph host processing hardware comprising means to translate a set of target instructions into instructions of a host instruction set, means to optimize the instructions of the host instruction set translated from the target application program speculating upon the occurrence of a condition, means to determine under control of the code morphing software official state of the target computer which existed at the beginning of a translation of a set of target instructions during execution of the target application program by the microprocessor, means for updating state of the target computer from state of the host computer when a set of host instructions executes in accordance

Abstract: Apparatus for use in a processing system having a host processor capable of executing a first instruction set to assist in running instructions of a different instruction set which is translated to the first instruction set by the host processor including circuitry for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor, circuitry for permanently storing memory stores temporarily stored when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor, and circuitry for eliminating memory stores temporarily stored when a determination is made that a sequence of translated instructions will generate an exception or error on the host processor.

Abstract: Apparatus and a method for storing data already stored at an often utilized memory address in registers local to a host processor and maintain the data in the registers and memory consistent so that the processor may respond more rapidly when a memory address is to be accessed.

Abstract: A memory controller for a microprocessor including apparatus to both detect a failure of speculation on the nature of the memory being addressed, and apparatus to recover from such failures.

Abstract: A memory architecture having particular application for use in computer systems employing virtual memory techniques. A processor provides row and column addresses to access data stored in a dynamic random access memory (DRAM). The virtual address supplied by the processor includes high and low order bits. In the present embodiment, the high order bits represent a virtual row address and the low order bits represent a real column address. The virtual row address is applied to a memory management unit (MMU) for translation into a real row address. The real column address need not be translated. A comparator compares the current virtual row address to the previous row address stored in a latch. If the current row and previous row addresses match, a cycle control circuit couples the real column address to the DRAM, and applies a strobe signal such that the desired data is accessed in the memory without the need to reapply the row address.