Abstract: A neural probe is presented for local neural optogenetics stimulation and neurochemistry recordings. The neural probe includes a probe body, a shank extending from the probe body to a tip, a plurality of micro light-emitting diodes (LEDs) positioned across a length of a first surface of the shank for providing neuron-affecting light, a plurality of carbon devices, and a plurality of carbon electrodes positioned across a length of a second surface of the shank, the second surface in opposed relation to the first surface. The plurality of carbon electrodes can be vertically aligned carbon nanotubes or vertically aligned carbon nanofibers. The plurality of carbon electrodes can also be horizontally aligned carbon nanotubes. The plurality of micro LEDs activate neurons and the plurality of vertically aligned carbon electrodes electrochemically record neurotransmitters.

Abstract: Fully integrated, on-chip DC-DC power converters are provided. In one aspect, a DC-DC power converter includes: a SOI wafer having a SOI layer separated from a substrate by a buried insulator, wherein the SOI layer and the buried insulator are selectively removed from at least one first portion of the SOI wafer, and wherein the SOI layer and the buried insulator remain present in at least one second portion of the SOI wafer; at least one GaN transistor formed on the substrate in the first portion of the SOI wafer; at least one CMOS transistor formed on the SOI layer in the second portion of the SOI wafer; a dielectric covering the GaN and CMOS transistors; and at least one magnetic inductor formed on the dielectric. A method of forming a fully integrated DC-DC power converter is also provided.

Abstract: Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.

Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.

Abstract: DC-DC power converters with GaN switches, magnetic inductors and CMOS power drivers integrated through face-to-face wafer bonding techniques are provided. In one aspect, an integrated DC-DC power converter includes: a Si CMOS chip having at least one Si CMOS transistor formed thereon; a GaN switch chip, bonded to the Si CMOS chip in a face-to-face manner, having at least one GaN transistor formed thereon; and an on-chip magnetic inductor present either on the Si CMOS chip or on the GaN switch chip. A method of forming an integrated DC-DC power converter is also provided.

Abstract: A neural probe is presented for local neural optogenetics stimulation and neurochemistry recordings. The neural probe includes a probe body, a shank extending from the probe body to a tip, a plurality of micro light-emitting diodes (LEDs) positioned across a length of a first surface of the shank for providing neuron-affecting light, a plurality of carbon devices, and a plurality of carbon electrodes positioned across a length of a second surface of the shank, the second surface in opposed relation to the first surface. The plurality of carbon electrodes can be vertically aligned carbon nanotubes or vertically aligned carbon nanofibers. The plurality of carbon electrodes can also be horizontally aligned carbon nanotubes. The plurality of micro LEDs activate neurons and the plurality of vertically aligned carbon electrodes electrochemically record neurotransmitters.

Abstract: Fully integrated, on-chip DC-DC power converters are provided. In one aspect, a DC-DC power converter includes: a SOI wafer having a SOI layer separated from a substrate by a buried insulator, wherein the SOI layer and the buried insulator are selectively removed from at least one first portion of the SOI wafer, and wherein the SOI layer and the buried insulator remain present in at least one second portion of the SOI wafer; at least one GaN transistor formed on the substrate in the first portion of the SOI wafer; at least one CMOS transistor formed on the SOI layer in the second portion of the SOI wafer; a dielectric covering the GaN and CMOS transistors; and at least one magnetic inductor formed on the dielectric. A method of forming a fully integrated DC-DC power converter is also provided.

Abstract: DC-DC power converters with GaN switches, magnetic inductors and CMOS power drivers integrated through face-to-face wafer bonding techniques are provided. In one aspect, an integrated DC-DC power converter includes: a Si CMOS chip having at least one Si CMOS transistor formed thereon; a GaN switch chip, bonded to the Si CMOS chip in a face-to-face manner, having at least one GaN transistor formed thereon; and an on-chip magnetic inductor present either on the Si CMOS chip or on the GaN switch chip. A method of forming an integrated DC-DC power converter is also provided.

Abstract: Techniques for integrating DC-DC power converters with other on-chip circuitry are provided. In one aspect, an integrated DC-DC power converter includes: a GaN transistor chip having at least one GaN switch formed thereon; an interposer chip, bonded to the GaN transistor chip, having at least one power driver transistor formed thereon; TSVs present in the interposer chip adjacent to the power driver transistor and which connect the power driver transistor to the GaN switch; and an on-chip magnetic inductor formed either on the GaN transistor chip or on the interposer chip. A method of forming a fully integrated DC-DC power converter is also provided.

Abstract: Fully integrated, on-chip DC-DC power converters are provided. In one aspect, a DC-DC power converter includes: a SOI wafer having a SOI layer separated from a substrate by a buried insulator, wherein the SOI layer and the buried insulator are selectively removed from at least one first portion of the SOI wafer, and wherein the SOI layer and the buried insulator remain present in at least one second portion of the SOI wafer; at least one GaN transistor formed on the substrate in the first portion of the SOI wafer; at least one CMOS transistor formed on the SOI layer in the second portion of the SOI wafer; a dielectric covering the GaN and CMOS transistors; and at least one magnetic inductor formed on the dielectric. A method of forming a fully integrated DC-DC power converter is also provided.

Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.

Abstract: Techniques for integrating DC-DC power converters with other on-chip circuitry are provided. In one aspect, an integrated DC-DC power converter includes: a GaN transistor chip having at least one GaN switch formed thereon; an interposer chip, bonded to the GaN transistor chip, having at least one power driver transistor formed thereon; TSVs present in the interposer chip adjacent to the power driver transistor and which connect the power driver transistor to the GaN switch; and an on-chip magnetic inductor formed either on the GaN transistor chip or on the interposer chip. A method of forming a fully integrated DC-DC power converter is also provided.

Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.

Abstract: Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.

Abstract: Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.

Abstract: Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a method of forming a semiconductor device includes: forming an outer trench in a silicon substrate, the forming exposing portions of the silicon substrate below an upper surface of the silicon substrate; depositing a dielectric liner layer inside the trench; depositing a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench in the silicon substrate; forming a silicide layer over a portion of the doped polysilicon layer; forming an intermediate contact layer within the inner trench; and forming a contact over a portion of the intermediate contact layer and a portion of the silicide layer.

Abstract: A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.

Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

Abstract: CMOS structures with a replacement substrate and methods of manufacture are disclosed herein. The method includes forming a device on a temporary substrate. The method further includes removing the temporary substrate. The method further includes bonding a permanent electrically insulative substrate to the device with a bonding structure.

Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.