Patents by Inventor Edoardo BREZZA

Edoardo BREZZA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162328
    Abstract: A bipolar transistor is manufactured by: forming a collector region; forming a first layer made of a material of a base region and an insulating second layer; forming a cavity reaching the collector region; forming a portion of the collector region and a portion of the base region in the cavity; forming an insulating fourth layer made of a same material as the insulating second layer in the periphery of the bottom of the cavity, the insulating fourth layer having a same thickness as the insulating second layer; forming an emitter region; and simultaneously removing the insulating second and a portion of the insulating fourth layer not covered by the emitter region.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 16, 2024
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER, Edoardo BREZZA, Nicolas GUITARD, Gregory AVENIER
  • Publication number: 20240162329
    Abstract: An electronic device includes an insulating first layer covering a second layer made of a doped semiconductor material. A cavity is formed to cross through the first layer and reach the second layer. Insulating spacers are forming against lateral walls of the cavity. A first doped semiconductor region fills the cavity. The first doped semiconductor region has a doping concentration decreasing from the second layer.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 16, 2024
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER, Edoardo BREZZA, Nicolas GUITARD
  • Patent number: 11798937
    Abstract: A bipolar transistor includes a collector region having a first doped portion located in a substrate and a second doped portion covering and in contact with an area of the first doped portion. The collector region has a doping profile having a peak in the first portion and a decrease from this peak up to in the second portion.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: October 24, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Edoardo Brezza, Alexis Gauthier
  • Patent number: 11710776
    Abstract: A bipolar transistor includes a stack of an emitter, a base, and a collector. The base is structured to have a comb shape including fingers oriented in a plane orthogonal to a stacking direction of the stack.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: July 25, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Edoardo Brezza, Pascal Chevalier
  • Publication number: 20230128033
    Abstract: According to one aspect provision is made of a method for ion implantation in a semiconductor wafer placed in an implantation chamber under vacuum, the semiconductor wafer having an integrated circuit area and a peripheral area around this integrated circuit area, the ion implantation allowing to apply a doping in regions, called implantation regions, of the integrated circuit area, the method comprising: forming a photosensitive resin coating serving as a mask on the semiconductor wafer, then forming openings in the photosensitive resin coating at said implantation regions of the integrated circuit area and at least at one region of the peripheral area, then implanting ions in the semiconductor wafer.
    Type: Application
    Filed: October 12, 2022
    Publication date: April 27, 2023
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Julien BORREL, Alexis GAUTHIER, Fanny HILARIO, Ludovic BERTHIER, Paul DUMAS, Edoardo BREZZA
  • Patent number: 11417756
    Abstract: A method of making a bipolar transistor includes forming a stack of a first, second, third and fourth insulating layers on a substrate. An opening is formed in the stack to reach the substrate. An epitaxial process forms the collector of the transistor on the substrate and selectively etches an annular opening in the third layer. The intrinsic part of the base is then formed by epitaxy on the collector, with the intrinsic part being separated from the third layer by the annular opening. The junction between the collector and the intrinsic part of the base is surrounded by the second layer. The emitter is formed on the intrinsic part and the third layer is removed. A selective deposition of a semiconductor layer on the second layer and in direct contact with the intrinsic part forms the extrinsic part of the base.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: August 16, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Edoardo Brezza, Alexis Gauthier, Fabien Deprat, Pascal Chevalier
  • Publication number: 20220122969
    Abstract: A bipolar transistor includes a collector region having a first doped portion located in a substrate and a second doped portion covering and in contact with an area of the first doped portion. The collector region has a doping profile having a peak in the first portion and a decrease from this peak up to in the second portion.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Edoardo BREZZA, Alexis GAUTHIER
  • Publication number: 20220059672
    Abstract: A bipolar transistor includes a stack of an emitter, a base, and a collector. The base is structured to have a comb shape including fingers oriented in a plane orthogonal to a stacking direction of the stack.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 24, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Edoardo BREZZA, Pascal CHEVALIER
  • Publication number: 20210273082
    Abstract: A method of making a bipolar transistor includes forming a stack of a first, second, third and fourth insulating layers on a substrate. An opening is formed in the stack to reach the substrate. An epitaxial process forms the collector of the transistor on the substrate and selectively etches an annular opening in the third layer. The intrinsic part of the base is then formed by epitaxy on the collector, with the intrinsic part being separated from the third layer by the annular opening. The junction between the collector and the intrinsic part of the base is surrounded by the second layer. The emitter is formed on the intrinsic part and the third layer is removed. A selective deposition of a semiconductor layer on the second layer and in direct contact with the intrinsic part forms the extrinsic part of the base.
    Type: Application
    Filed: February 15, 2021
    Publication date: September 2, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Edoardo BREZZA, A;exos GAUTHIER, Fabien DEPRAT, Pascal CHEVALIER