Abstract: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied.

Abstract: A computing system that uses a Scale-Out NUMA (“soNUMA”) architecture, programming model, and/or communication protocol provides for low-latency, distributed in-memory processing. Using soNUMA, a programming model is layered directly on top of a NUMA memory fabric via a stateless messaging protocol. To facilitate interactions between the application, OS, and the fabric, soNUMA uses a remote memory controller—an architecturally-exposed hardware block integrated into the node's local coherence hierarchy.

Abstract: According to one aspect of the invention, a request to generate a state checkpoint of a computer is initiated within a user-level software entity, such as a virtual machine. Upon sensing the request, a checkpointing mechanism generates and stores at least one checkpoint, each checkpoint comprising a representation of the total state of the computer system. Upon sensing a state restoration request corresponding to one of the checkpoints, the checkpointing mechanism restores the checkpointed state in the computer, which can then resume operation from the restored total state. According to another aspect of the invention, a total checkpointed state is exported to another computer, where the state can be modified, for example, debugged, and then loaded into either the originally checkpointed computer (which, again, may be a virtual machine), or some other computer.

Abstract: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied.

Abstract: According to one aspect of the invention, a request to generate a state checkpoint of a computer is initiated within a user-level software entity, such as a virtual machine. Upon sensing the request, a checkpointing mechanism generates and stores at least one checkpoint, each checkpoint comprising a representation of the total state of the computer system. Upon sensing a state restoration request corresponding to one of the checkpoints, the checkpointing mechanism restores the checkpointed state in the computer, which can then resume operation from the restored total state. According to another aspect of the invention, a total checkpointed state is exported to another computer, where the state can be modified, for example, debugged, and then loaded into either the originally checkpointed computer (which, again, may be a virtual machine), or some other computer.

Abstract: A source computer system with one instruction set architecture (ISA) configured to run on a target hardware system that has its own ISA. During execution from binary translation, synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system, and asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied. The system also includes subsystems, and related methods of operation, for detecting the occurrence of all of these types of exceptions, to handle them, and to do so with precise reentry into the interrupted instruction stream. The binary translation and exception-handling subsystems are included as components of a virtual machine monitor which is installed between the target hardware system and the source system.

Abstract: A computing system that uses a Scale-Out NUMA (“soNUMA”) architecture, programming model, and/or communication protocol provides for low-latency, distributed in-memory processing. Using soNUMA, a programming model is layered directly on top of a NUMA memory fabric via a stateless messaging protocol. To facilitate interactions between the application, OS, and the fabric, soNUMA uses a remote memory controller—an architecturally-exposed hardware block integrated into the node's local coherence hierarchy.

Abstract: According to one aspect of the invention, a request to generate a state checkpoint of a computer is initiated within a user-level software entity, such as a virtual machine. Upon sensing the request, a checkpointing mechanism generates and stores at least one checkpoint, each checkpoint comprising a representation of the total state of the computer system. Upon sensing a state restoration request corresponding to one of the checkpoints, the checkpointing mechanism restores the checkpointed state in the computer, which can then resume operation from the restored total state. According to another aspect of the invention, a total checkpointed state is exported to another computer, where the state can be modified, for example, debugged, and then loaded into either the originally checkpointed computer (which, again, may be a virtual machine), or some other computer.

Abstract: According to one aspect of the invention, a request to generate a state checkpoint of a computer is initiated within a user-level software entity, such as a virtual machine. Upon sensing the request, a checkpointing mechanism generates and stores at least one checkpoint, each checkpoint comprising a representation of the total state of the computer system. Upon sensing a state restoration request corresponding to one of the checkpoints, the checkpointing mechanism restores the checkpointed state in the computer, which can then resume operation from the restored total state. According to another aspect of the invention, a total checkpointed state is exported to another computer, where the state can be modified, for example, debugged, and then loaded into either the originally checkpointed computer (which, again, may be a virtual machine), or some other computer.

Abstract: I/O operations between a virtual machine (VM) and a device external to the VM are monitored by a virtual machine monitor (VMM). Data passing between the VM and the external device is transformed by the VMM, in some cases only when a predetermined filtering or triggering condition is met. Because the VMM, and thus the transformation operation, is transparent to the VM, the transformation cannot be prevented or undone or even affected by any action by a user of the VM. Examples of the non-defeatable transformation of I/O data include generating display overlays such as banners, masking out portions of a display, encryption, compression and network shaping such as bandwidth limiting.

Abstract: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied.

Abstract: I/O operations between a virtual machine (VM) and a device external to the VM are monitored by a virtual machine monitor (VMM). Data passing between the VM and the external device is transformed by the VMM, in some cases only when a predetermined filtering or triggering condition is met. Because the VMM, and thus the transformation operation, is transparent to the VM, the transformation cannot be prevented or undone or even affected by any action by a user of the VM. Examples of the non-defeatable transformation of I/O data include generating display overlays such as banners, masking out portions of a display, encryption, compression and network shaping such as bandwidth limiting.

Abstract: I/O operations between a virtual machine (VM) and a device external to the VM are monitored by a virtual machine monitor (VMM). Data passing between the VM and the external device is transformed by the VMM, in some cases only when a predetermined filtering or triggering condition is met. Because the VMM, and thus the transformation operation, is transparent to the VM, the transformation cannot be prevented or undone or even affected by any action by a user of the VM. Examples of the non-defeatable transformation of I/O data include generating display overlays such as banners, masking out portions of a display, encryption, compression and network shaping such as bandwidth limiting.

Abstract: The invention virtualizes a computer that includes a host computer system, which comprises a processor, memory, and physical system devices. A conventional operating system (referred to below as the “host operating system” or “HOS”) is installed on the hardware. A computer program product that is executable within the host computer system comprises computer-executable code for implementing an interface software layer, preferably a virtual machine monitor, between the host system and a virtual machine; for reading in and storing state information of the processor associated with the HOS; and for logically decoupling the HOS from the processor with respect to pre-determined functions of the interface software layer and the virtual machine by setting the processor state information to settings associated with the interface software layer.

Abstract: According to one aspect of the invention, a request to generate a state checkpoint of a computer is initiated within a user-level software entity, such as a virtual machine. Upon sensing the request, a checkpointing mechanism generates and stores at least one checkpoint, each checkpoint comprising a representation of the total state of the computer system. Upon sensing a state restoration request corresponding to one of the checkpoints, the checkpointing mechanism restores the checkpointed state in the computer, which can then resume operation from the restored total state. According to another aspect of the invention, a total checkpointed state is exported to another computer, where the state can be modified, for example, debugged, and then loaded into either the originally checkpointed computer (which, again, may be a virtual machine), or some other computer.

Abstract: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied.

Abstract: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied.

Abstract: I/O operations between a virtual machine (VM) and a device external to the VM are monitored by a virtual machine monitor (VMM). Data passing between the VM and the external device is transformed by the VMM, in some cases only when a predetermined filtering or triggering condition is met. Because the VMM, and thus the transformation operation, is transparent to the VM, the transformation cannot be prevented or undone or even affected by any action by a user of the VM. Examples of the non-defeatable transformation of I/O data include generating display overlays such as banners, masking out portions of a display, encryption, compression and network shaping such as bandwidth limiting.

Abstract: A computer system includes at least one virtual machine that has a plurality of virtual processors all running on an underlying hardware platform. A software interface layer such as a virtual machine monitor establishes traces on primary structures located in a common memory space as needed for the different virtual processors. Whenever any one of the virtual processors generates a trace event, such as accessing a traced structure, then a notification is sent to at least the other virtual processors that have a trace on the accessed primary structure. In some applications, the VMM derives and maintains secondary structures corresponding to the primary structures, such as where the VMM converts, through binary translation, original code intended to run on a virtual processor into code that can be run on an underlying physical processor of the hardware platform. In these applications, the VMM may rederive or invalidate the secondary structures as needed upon receipt of the notification of the trace event.

Abstract: A virtual machine monitor (VMM) is included in a computer system that has a protected host operating system (HOS). A virtual machine running at least one application via a virtual operating system is connected to the VMM. Both the HOS and the VMM have separate operating contexts and disjoint address spaces, but are both co-resident at system level. A driver that is downloadable into the HOS at system level forms a total context switch between the VMM and HOS contexts. A user-level emulator accepts commands from the VMM via the system-level driver and processes these commands as remote procedure calls. The emulator is able to issue host operating system calls and thereby access the physical system devices via the host operating system. The host operating system itself thus handles execution of certain VMM instructions, such as accessing physical devices.