Patents by Inventor Eduardas JODKA
Eduardas JODKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11804769Abstract: In some examples, an apparatus includes a driver having a driver output, a capacitor having a first plate and a second plate, the first plate coupled to the driver output, and a transistor having a transistor gate, a transistor source, and a transistor drain. The apparatus also includes a first switch coupled between the second plate and the transistor gate, a second switch coupled between the second plate and the transistor drain, and a third switch coupled between the transistor gate and the transistor drain.Type: GrantFiled: December 30, 2020Date of Patent: October 31, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Eduardas Jodka, Gaetano Maria Walter Petrina, Manuel Wiersch
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Patent number: 11695342Abstract: An active pull-up circuit which is operated between an upper voltage and a lower voltage and which pulls up an intermediate node to the upper voltage in reaction to an input voltage of the pull-up circuit falling from the upper voltage to an intermediate voltage is described. The pull-up circuit comprises a first transistor having a source terminal coupled to the upper voltage, a drain terminal coupled to the intermediate node and a gate terminal coupled to the input voltage. The pull-up circuit comprises a second transistor having a source terminal coupled to the upper voltage, a drain terminal coupled to the intermediate node and a gate terminal coupled to a control node. In addition, the pull-up circuit comprises control circuitry configured to pull the control node to a voltage level of the intermediate node, subject to the input voltage falling from the upper voltage to the intermediate voltage.Type: GrantFiled: July 15, 2021Date of Patent: July 4, 2023Assignee: Dialog Semiconductor (UK) LimitedInventor: Eduardas Jodka
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Patent number: 11563378Abstract: A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator cirType: GrantFiled: August 24, 2020Date of Patent: January 24, 2023Assignee: Texas Instruments IncorporatedInventors: Julian Becker, Christian Harder, Eduardas Jodka, Stefan Dietrich, Puneet Sareen
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Publication number: 20230015995Abstract: An active pull-up circuit which is operated between an upper voltage and a lower voltage and which pulls up an intermediate node to the upper voltage in reaction to an input voltage of the pull-up circuit falling from the upper voltage to an intermediate voltage is described. The pull-up circuit comprises a first transistor having a source terminal coupled to the upper voltage, a drain terminal coupled to the intermediate node and a gate terminal coupled to the input voltage. The pull-up circuit comprises a second transistor having a source terminal coupled to the upper voltage, a drain terminal coupled to the intermediate node and a gate terminal coupled to a control node. In addition, the pull-up circuit comprises control circuitry configured to pull the control node to a voltage level of the intermediate node, subject to the input voltage falling from the upper voltage to the intermediate voltage.Type: ApplicationFiled: July 15, 2021Publication date: January 19, 2023Inventor: Eduardas Jodka
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Publication number: 20220209654Abstract: In some examples, an apparatus includes a driver having a driver output, a capacitor having a first plate and a second plate, the first plate coupled to the driver output, and a transistor having a transistor gate, a transistor source, and a transistor drain. The apparatus also includes a first switch coupled between the second plate and the transistor gate, a second switch coupled between the second plate and the transistor drain, and a third switch coupled between the transistor gate and the transistor drain.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Inventors: Eduardas JODKA, Gaetano Maria Walter PETRINA, Manuel WIERSCH
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Patent number: 11196339Abstract: A switching converter having a voltage input, a voltage output and a transistor connected between the voltage input and the voltage output, the switching converter including a control circuit comprising: a gate driver having an input, a first voltage supply input, a second voltage supply input and an output operable to be connected to a control terminal of the transistor; a bootstrap capacitor connected between the first voltage supply input and the second voltage supply input; and a charge pump having an input operable to be connected to the voltage input and an output connected to the first voltage supply input.Type: GrantFiled: December 16, 2020Date of Patent: December 7, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Eduardas Jodka, Julian Becker Ferreira, Christian Harder, Florian Schimkat
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Patent number: 11056966Abstract: A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.Type: GrantFiled: August 18, 2020Date of Patent: July 6, 2021Assignee: Texas Instruments IncorporatedInventors: Eduardas Jodka, Julian Becker, Carsten Stoerk
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Publication number: 20210083583Abstract: A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator cirType: ApplicationFiled: August 24, 2020Publication date: March 18, 2021Inventors: Julian Becker, Christian Harder, Eduardas Jodka, Stefan Dietrich, Puneet Sareen
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Patent number: 10871810Abstract: A power supply system can include at least one power switch to generate an output current based on an input voltage in response to a switching signal to generate an output voltage. A feedback system generates a feedback current based on the output voltage. A mode detector generates a control current associated with the output current based on the feedback current and selects between a pulse-width modulation (PWM) mode and a pulse mode based on an amplitude of the control current. The PWM mode is associated with a sequential on-time and off-time of the at least one power switch, and the pulse mode is associated with adding an idle time between the on-time and the off-time of the at least one power switch based on the switching signal. A gate driver system generates the switching signal based on the mode.Type: GrantFiled: August 21, 2018Date of Patent: December 22, 2020Assignee: Texas Instruments IncorporatedInventors: Joerg Kirchner, Stefan Dietrich, Julian Becker, Eduardas Jodka
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Publication number: 20200381990Abstract: A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.Type: ApplicationFiled: August 18, 2020Publication date: December 3, 2020Inventors: Eduardas Jodka, Julian Becker, Carsten Stoerk
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Patent number: 10784764Abstract: A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.Type: GrantFiled: February 1, 2019Date of Patent: September 22, 2020Assignee: Texas Instruments IncorporatedInventors: Eduardas Jodka, Julian Becker, Carsten Stoerk
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Publication number: 20200251976Abstract: A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.Type: ApplicationFiled: February 1, 2019Publication date: August 6, 2020Inventors: Eduardas Jodka, Julian Becker, Carsten Stoerk
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Patent number: 10673337Abstract: A switch-node rising edge detection circuit is provided for a switched-mode DC/DC boost converter. A high-side gate-driver couples a gate of the high-side NMOS power transistor to either a first terminal of a bootstrap capacitor or the switch-node. The detection circuit includes an AND gate that receives an activation signal on a first input and provides a switching signal to the high-side gate-driver. A PMOS transistor is coupled in series with an inverter between the first terminal of the bootstrap capacitor and a second input of the AND gate. The inverter receives supply voltages from the first terminal of the bootstrap capacitor and the switch-node. The gate of the PMOS transistor receives the activation signal. An NMOS transistor is coupled between an output voltage and a node between the PMOS transistor and the inverter. A gate of the NMOS transistor is coupled to the bootstrap capacitor's first terminal.Type: GrantFiled: February 1, 2019Date of Patent: June 2, 2020Assignee: Texas Instruments IncorporatedInventors: Eduardas Jodka, Julian Becker, Stefan Dietrich
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Publication number: 20200064893Abstract: A power supply system can include at least one power switch to generate an output current based on an input voltage in response to a switching signal to generate an output voltage. A feedback system generates a feedback current based on the output voltage. A mode detector generates a control current associated with the output current based on the feedback current and selects between a pulse-width modulation (PWM) mode and a pulse mode based on an amplitude of the control current. The PWM mode is associated with a sequential on-time and off-time of the at least one power switch, and the pulse mode is associated with adding an idle time between the on-time and the off-time of the at least one power switch based on the switching signal. A gate driver system generates the switching signal based on the mode.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: JOERG KIRCHNER, STEFAN DIETRICH, JULIAN BECKER, EDUARDAS JODKA
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Patent number: 10498315Abstract: A level shifter with reduced propagation delay. A level shifter includes a signal input terminal, a first signal output node, a first transistor, a second transistor, a third transistor, and a first capacitor. The first transistor includes a control terminal coupled to the signal input terminal. The second transistor includes an output terminal coupled to an input terminal of the first transistor. The first capacitor includes a bottom plate coupled to an input terminal of the second transistor. The third transistor includes a control terminal coupled to a top plate of the first capacitor, and an output terminal coupled to the first signal output node.Type: GrantFiled: March 5, 2018Date of Patent: December 3, 2019Assignee: Texas Instruments IncorporatedInventors: Eduardas Jodka, Julian Becker
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Publication number: 20190273485Abstract: A level shifter with reduced propagation delay. A level shifter includes a signal input terminal, a first signal output node, a first transistor, a second transistor, a third transistor, and a first capacitor. The first transistor includes a control terminal coupled to the signal input terminal. The second transistor includes an output terminal coupled to an input terminal of the first transistor. The first capacitor includes a bottom plate coupled to an input terminal of the second transistor. The third transistor includes a control terminal coupled to a top plate of the first capacitor, and an output terminal coupled to the first signal output node.Type: ApplicationFiled: March 5, 2018Publication date: September 5, 2019Inventors: Eduardas JODKA, Julian BECKER