Patents by Inventor Edvard Sorgard

Edvard Sorgard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230385106
    Abstract: A fault detection scheme for a data processor that comprises a programmable execution unit operable to execute programs to perform processing operations, and in which when executing a program, the execution unit executes the program for respective execution threads, each execution thread corresponding to a respective work item. In order to detect faults, a set of two or more identical execution threads is generated. The identical execution threads when executed perform identical processing for the same work item and a result of the processing of the same work item can thus be compared to determine whether there is a fault associated with the data processor.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 30, 2023
    Inventors: Isidoros Sideris, Daren Croxford, Edvard Sorgard
  • Patent number: 11308573
    Abstract: A device includes a processor and memory. The memory has stored thereon a plurality of executable instructions. The executable instructions, when executed by the processor, cause the processor to: receive an access request affecting an operation of the device; facilitate encryption and/or authentication across an interface coupled to the device, wherein the interface is configured to secure the access request; and execute the access request.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: April 19, 2022
    Assignee: ARM Norway AS
    Inventors: Jorn Nystad, Edvard Sorgard, Borgar Ljosland, Mario Blazevic
  • Patent number: 11188999
    Abstract: A slave device communicates with a host system via a host communications bus. The host system includes one processing unit that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processing unit and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical addresses of the slave's resources and forwards the accesses to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: November 30, 2021
    Assignee: ARM NORWAY AS
    Inventors: Jorn Nystad, Edvard Sorgard, Borgar Ljosland, Mario Blazevic
  • Patent number: 10755473
    Abstract: When rendering a scene that includes a complex object made up of many individual primitives, rather than processing each primitive making up the object in turn, a bounding volume which surrounds the complex object is generated and the scene is then processed using the bounding volume in place of the actual primitives making up the complex object. If it is determined that the bounding volume representation of the object will be completely occluded in the scene (e.g. by a foreground object), then the individual primitives making up the complex object are not processed. This can save significantly on processing time and resources for the scene.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: August 25, 2020
    Assignee: ARM Limited
    Inventors: Jorn Nystad, Borgar Ljosland, Edvard Sorgard
  • Patent number: 10657681
    Abstract: A scene to be rendered is divided into plural individual sub-regions or tiles. The individual sub-regions 51 are also grouped into differing groups of sets of plural sub-regions. There is a top level layer comprising a set of 8×8 sub-regions which encompasses the entire scene area. There is then a group of four 4×4 sets of sub-regions, then a group of sixteen 2×2 sets of sub-regions, and finally a layer comprising the 64 single sub-regions. A primitive list building processor takes each primitive in turn, determines a location for that primitive, compares the primitive's location with the locations of the sub-regions and the locations of the sets of sub-regions, and allocates the primitive to respective primitive lists for the sub-regions and sets of sub-regions accordingly.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: May 19, 2020
    Assignee: ARM NORWAY AS
    Inventors: Edvard Sorgard, Borgar Ljosland, Jorn Nystad, Mario Blazevic, Frank Langtind
  • Publication number: 20190278717
    Abstract: A slave device communicates with a host system via a host communications bus. The host system includes one processing unit that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processing unit and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical addresses of the slave's resources and forwards the accesses to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Inventors: Jorn NYSTAD, Edvard SORGARD, Borgar LJOSLAND, Mario BLAZEVIC
  • Patent number: 10331574
    Abstract: A slave device communicates with a host system via a host communications bus. The host system includes one processing unit that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processing unit and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical address of the slave's resources and forwards the access to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: June 25, 2019
    Assignee: ARM Norway AS
    Inventors: Jorn Nystad, Edvard Sorgard, Borgar Ljosland, Mario Blazevic
  • Patent number: 10223288
    Abstract: A slave device communicates with a host system via a host communications bus. The host system includes one processor that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processor and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical addresses of the slave's resources and forwards the accesses to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: March 5, 2019
    Assignee: ARM NORWAY AS
    Inventors: Jorn Nystad, Edvard Sorgard, Borgar Ljosland, Mario Blazevic
  • Publication number: 20180293765
    Abstract: A scene to be rendered is divided into plural individual sub-regions or tiles. The individual sub-regions 51 are also grouped into differing groups of sets of plural sub-regions. There is a top level layer comprising a set of 8×8 sub-regions which encompasses the entire scene area. There is then a group of four 4×4 sets of sub-regions, then a group of sixteen 2×2 sets of sub-regions, and finally a layer comprising the 64 single sub-regions. A primitive list building processor takes each primitive in turn, determines a location for that primitive, compares the primitive's location with the locations of the sub-regions and the locations of the sets of sub-regions, and allocates the primitive to respective primitive lists for the sub-regions and sets of sub-regions accordingly.
    Type: Application
    Filed: June 13, 2018
    Publication date: October 11, 2018
    Inventors: Edvard Sorgard, Borgar LJOSLAND, Jorn NYSTAD, Mario BLAZEVIC, Frank LANGTIND
  • Publication number: 20180197326
    Abstract: When rendering a scene that includes a complex object made up of many individual primitives, rather than processing each primitive making up the object in turn, a bounding volume which surrounds the complex object is generated and the scene is then processed using the bounding volume in place of the actual primitives making up the complex object. If it is determined that the bounding volume representation of the object will be completely occluded in the scene (e.g. by a foreground object), then the individual primitives making up the complex object are not processed. This can save significantly on processing time and resources for the scene.
    Type: Application
    Filed: March 7, 2018
    Publication date: July 12, 2018
    Inventors: Jorn NYSTAD, Borgar LJOSLAND, Edvard SORGARD
  • Patent number: 10019820
    Abstract: A scene to be rendered is divided into plural individual sub-regions or tiles. The individual sub-regions 51 are also grouped into differing groups of sets of plural sub-regions. There is a top level layer comprising a set of 8×8 sub-regions which encompasses the entire scene area. There is then a group of four 4×4 sets of sub-regions, then a group of sixteen 2×2 sets of sub-regions, and finally a layer comprising the 64 single sub-regions. A primitive list building processor takes each primitive in turn, determines a location for that primitive, compares the primitive's location with the locations of the sub-regions and the locations of the sets of sub-regions, and allocates the primitive to respective primitive lists for the sub-regions and sets of sub-regions accordingly.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: July 10, 2018
    Assignee: ARM NORWAY AS
    Inventors: Edvard Sorgard, Borgar Ljosland, Jorn Nystad, Mario Blazevic, Frank Langtind
  • Patent number: 9965886
    Abstract: A graphics processor includes a graphics object list building unit that determines the location of each draw call in a scene to be rendered and generates a list of draw calls for each sub-region (tile) that the scene to be rendered is divided into. The draw call lists are stored in a memory. A graphics object selection unit of a renderer of the graphics processor then determines which draw call is to be rendered next by considering the draw call list stored in the memory for the sub-region (tile) of the scene that is currently being rendered.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: May 8, 2018
    Assignee: ARM Norway AS
    Inventors: Edvard Sorgard, Borgar Ljosland, Jorn Nystad, Mario Blazevic, Frank Langtind
  • Patent number: 9947131
    Abstract: When rendering a scene that includes a complex object made up of many individual primitives, rather than processing each primitive making up the object in turn, a bounding volume which surrounds the complex object is generated and the scene is then processed using the bounding volume in place of the actual primitives making up the complex object. If it is determined that the bounding volume representation of the object will be completely occluded in the scene (e.g. by a foreground object), then the individual primitives making up the complex object are not processed. This can save significantly on processing time and resources for the scene.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: April 17, 2018
    Assignee: ARM Limited
    Inventors: Jorn Nystad, Borgar Ljosland, Edvard Sorgard
  • Patent number: 9659401
    Abstract: A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. Each page of a graphics texture has an associated fade factor value that can be set by an application that is to use the texture to control the contribution that the page will be used to make to any texturing result that is generated using the texture page in question. The graphics processing system then controls the contribution of texture data from a texture page to texturing result data to be generated in accordance with the fade factor value associated with the texture page in question. This allows texture paging to be done in a more visually pleasing manner than just a binary “page-is-here”/“page-is-not-here” switch.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: May 23, 2017
    Assignee: ARM LIMITED
    Inventors: Jorn Nystad, Andreas Engh-Halstvedt, Edvard Sorgard, Thomas Jeremy Olson, Marius Bjorge
  • Patent number: 9472018
    Abstract: In a tile-based graphics processing system, when an overlay image is to be rendered onto an existing image, the existing tile data for the existing image from the frame buffer in the main memory is pre-loaded into the local color buffer of the graphics processor (step 41). The overlay content is then rendered and used to modify the tile data stored in the color buffer (step 44). When the data for a given sampling position stored in the tile buffer is modified as a result of the overlay image, a corresponding dirty bit for the tile region that the sampling position falls within is set (step 45). Then, when all the rendering for the tile has been completed, the dirty bits are examined to determine which regions of the tile have been modified (step 46). The modified tile regions are written back to the output image in the frame buffer in the main memory (step 47), but any regions whose dirty bits have not been set are not written back to the frame buffer in the main memory.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: October 18, 2016
    Assignee: ARM LIMITED
    Inventors: Andreas Engh-Halstvedt, Jorn Nystad, Edvard Sorgard, Frode Heggelund
  • Publication number: 20160283408
    Abstract: A device includes a processor and memory. The memory has stored thereon a plurality of executable instructions. The executable instructions, when executed by the processor, cause the processor to: receive an access request affecting an operation of the device; facilitate encryption and/or authentication across an interface coupled to the device, wherein the interface is configured to secure the access request; and execute the access request.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 29, 2016
    Inventors: Jorn NYSTAD, Edvard SORGARD, Borgar LJOSLAND, Mario BLAZEVIC
  • Publication number: 20160267709
    Abstract: When rendering a scene that includes a complex object made up of many individual primitives, rather than processing each primitive making up the object in turn, a bounding volume which surrounds the complex object is generated and the scene is then processed using the bounding volume in place of the actual primitives making up the complex object. If it is determined that the bounding volume representation of the object will be completely occluded in the scene (e.g. by a foreground object), then the individual primitives making up the complex object are not processed. This can save significantly on processing time and resources for the scene.
    Type: Application
    Filed: May 23, 2016
    Publication date: September 15, 2016
    Inventors: Jorn NYSTAD, Borgar LJOSLAND, Edvard SORGARD
  • Patent number: 9367953
    Abstract: When rendering a scene that includes a complex object made up of many individual primitives, rather than processing each primitive making up the object in turn, a bounding volume which surrounds the complex object is generated and the scene is then processed using the bounding volume in place of the actual primitives making up the complex object. If it is determined that the bounding volume representation of the object will be completely occluded in the scene (e.g. by a foreground object), then the individual primitives making up the complex object are not processed. This can save significantly on processing time and resources for the scene.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: June 14, 2016
    Assignee: ARM Limited
    Inventors: Jørn Nystad, Borgar Ljosland, Edvard Sørgård
  • Patent number: 9349210
    Abstract: A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. If the texture page that is required for performing a texturing operation at an originally desired level of detail (52) is not present in the local memory of the graphics processing system (53), the virtual texture lookup process loops back to try to sample the texture at an increased level of detail (55), and so on, until texture data that can be used is found in the local memory of the graphics processing system (53). This allows the texturing operation to proceed using texture data for the texel positions in question from a higher level (less detailed) mipmap in place of the originally desired texture data.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: May 24, 2016
    Assignee: ARM LIMITED
    Inventors: Jorn Nystad, Andreas Engh-Halstvedt, Edvard Sorgard, Thomas Jeremy Olson, Marius Bjorge
  • Publication number: 20160005195
    Abstract: A scene to be rendered is divided into plural individual sub-regions or tiles. The individual sub-regions 51 are also grouped into differing groups of sets of plural sub-regions. There is a top level layer comprising a set of 8×8 sub-regions which encompasses the entire scene area. There is then a group of four 4×4 sets of sub-regions, then a group of sixteen 2×2 sets of sub-regions, and finally a layer comprising the 64 single sub-regions. A primitive list building processor takes each primitive in turn, determines a location for that primitive, compares the primitive's location with the locations of the sub-regions and the locations of the sets of sub-regions, and allocates the primitive to respective primitive lists for the sub-regions and sets of sub-regions accordingly.
    Type: Application
    Filed: September 15, 2015
    Publication date: January 7, 2016
    Inventors: Edvard Sorgard, Borgar LJOSLAND, Jorn NYSTAD, Mario BLAZEVIC, Frank LANGTIND