Abstract: A processor includes an instruction issue circuit, and high-utilization and low-utilization execution unit circuits coupled to execute instructions received from the instruction issue unit. On average, utilization of the low-utilization execution unit circuit is lower than utilization of the high-utilization execution unit circuit. The processor also includes a retention circuit coupled to a different power domain than the low-utilization execution unit circuit, and a power management circuit.

Abstract: Embodiments of a multiplier unit that may be used for division and square root operations are disclosed. The embodiments may provide a reduced and fixed latency for denormalization and rounding used in the division and square root operations. A storage circuit may be configured to receive first and second source operands. A multiplier circuit may be configured to perform a plurality of multiplication operations dependent upon the first and second source operands. Each result after an initial result of the multiplier may also depend on at least one previous result. Circuitry may be configured to perform a shift operation and a rounding operation on a given result of the plurality of results. An error of the given result may be less than a predetermined threshold value.

Abstract: In an embodiment, an integrated circuit may include one or more power gated blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power gated block and a block enable clock. The power gated block may generate local block enables to various power switch segments in the power gated block. In particular, the power gated block may include a set of series-connected flops that receive the block enable from the power manager circuit. The power gated block may include a set of multiplexors (muxes) that provide the local block enables for each power switch segment. One input of the muxes is coupled to the block enable, and the other input is coupled to another enable propagated through one of the other power switch segments. Accordingly, the muxes may be controlled to select the propagated enables or the input block enable.

Abstract: In an embodiment, an integrated circuit may include one or more power gated blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power gated block and a block enable clock. The power gated block may generate local block enables to various power switch segments in the power gated block. In particular, the power gated block may include a set of series-connected flops that receive the block enable from the power manager circuit. The power gated block may include a set of multiplexors (muxes) that provide the local block enables for each power switch segment. One input of the muxes is coupled to the block enable, and the other input is coupled to another enable propagated through one of the other power switch segments. Accordingly, the muxes may be controlled to select the propagated enables or the input block enable.

Abstract: Embodiments of a multiplier unit that may be used for division and square root operations are disclosed. The embodiments may provide a reduced and fixed latency for denormalization and rounding used in the division and square root operations. A storage circuit may be configured to receive first and second source operands. A multiplier circuit may be configured to perform a plurality of multiplication operations dependent upon the first and second source operands. Each result after an initial result of the multiplier may also depend on at least one previous result. Circuitry may be configured to perform a shift operation and a rounding operation on a given result of the plurality of results. An error of the given result may be less than a predetermined threshold value.

Abstract: The invention relates to a method for carrier recovery of an equalized communications signal in a multiple-input multiple-output communications system. The method is comprised of the steps generating a phase rotation estimate from the equalized communications signal and a demodulated signal estimate of the equalized communications signal, and adjusting at least one of the phase and frequency of the equalized communications signal based on the phase rotation estimate. The step of generating the phase rotation estimate further comprising using a model based filter with the equalized communications signal as input signal to the model based filter and the demodulated signal estimate as a measurement to the model based filter.

Abstract: The invention relates to a method for carrier recovery of an equalized communications signal in a multiple-input multiple-output communications system. The method is comprised of the steps generating a phase rotation estimate from the equalized communications signal and a demodulated signal estimate of the equalized communications signal, and adjusting at least one of the phase and frequency of the equalized communications signal based on the phase rotation estimate. The step of generating the phase rotation estimate further comprising using a model based filter with the equalized communications signal as input signal to the model based filter and the demodulated signal estimate as a measurement to the model based filter.

Abstract: A memory arrangement is provided having a plurality of memory elements, the elements being associated with a memory space that can be addressed in a row and column fashion during a write or a read access. The memory arrangement further includes a first macro bank comprising a first plurality of memory cells comprising a first subset of the memory elements and a second macro bank comprising a second plurality of memory cells comprising a second subset of the memory elements. The memory arrangement further includes an address resolution stage for addressing the memory cells in the respective macro banks. The memory cells are arranged so that the memory space is partitioned into a plurality of non-overlapping basic matrices, whereby each basic matrix is mapped to a given macro bank and wherein the memory cells are arranged logically so that the memory space is partitioned into a plurality of non-overlapping logic matrices of a given size, each logic matrix being of a size equal or larger than a basic matrix.

Abstract: A memory arrangement is provided having a plurality of memory elements, the elements being associated with a memory space that can be addressed in a row and column fashion during a write or a read access. The memory arrangement further includes a first macro bank comprising a first plurality of memory cells comprising a first subset of the memory elements and a second macro bank comprising a second plurality of memory cells comprising a second subset of the memory elements. The memory arrangement further includes an address resolution stage for addressing the memory cells in the respective macro banks. The memory cells are arranged so that the memory space is partitioned into a plurality of non-overlapping basic matrices, whereby each basic matrix is mapped to a given macro bank and wherein the memory cells are arranged logically so that the memory space is partitioned into a plurality of non-overlapping logic matrices of a given size, each logic matrix being of a size equal or larger than a basic matrix.