Patents by Inventor Edward B. Harris
Edward B. Harris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100061036Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.Type: ApplicationFiled: November 10, 2009Publication date: March 11, 2010Inventors: Edward B. Harris, Canzhong He, Che Choi Leung, Bruce W. McNeill
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Patent number: 7635888Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.Type: GrantFiled: November 2, 2005Date of Patent: December 22, 2009Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Canzhong He, Che Choi Leung, Bruce W. McNeill
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Publication number: 20090273012Abstract: A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first capacitor having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and adjusting a ratio of the first capacitance value and a second capacitance value associated with the MOS device such that a second signal present at the gate of the MOS device will be an attenuated version of the first signal. An amount of attenuation of the first signal is a function of the ratio of the first and second capacitance values.Type: ApplicationFiled: April 30, 2008Publication date: November 5, 2009Inventor: Edward B. Harris
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Publication number: 20090059684Abstract: An apparatus and method for forming a write-once non-volatile memory cell. A memory cell comprises a first and a second MOSFET, wherein the first MOSFET undergoes a process to modify the threshold voltage such that a modified threshold voltage represents a first stored logic value. By determining which one of the first and the second MOSFETS has an altered threshold voltage, the stored logic value is determinable. The threshold voltage of the first MOSFET is altered by supplying current through a MOSFET gate, causing a gate heating effect that results in a threshold voltage shift.Type: ApplicationFiled: October 30, 2008Publication date: March 5, 2009Applicant: Agere Systems Inc.Inventor: Edward B. Harris
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Publication number: 20090029490Abstract: It has been found that for silicon integrated circuits having capacitor structures or other p-n junctions structure at a technology node of 32 nm or smaller, photovoltaic induced corrosion of copper in the metallization stack is a significant issue. Thus processing conditions or device configurations are employed that preclude such corrosion. In one embodiment photovoltaic induced corrosion is monitored to prevent completion of devices with corrosion defects.Type: ApplicationFiled: July 22, 2008Publication date: January 29, 2009Inventors: Frank A. Baiocchi, James Thomas Cargo, John Michael DeLucca, Edward B. Harris
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Patent number: 7457180Abstract: An apparatus and method for forming a write-once non-volatile memory cell. A memory cell comprises a first and a second MOSFET, wherein the first MOSFET undergoes a process to modify the threshold voltage such that a modified threshold voltage represents a first stored logic value. By determining which one of the first and the second MOSFETS has an altered threshold voltage, the stored logic value is determinable. The threshold voltage of the first MOSFET is altered by supplying current through a MOSFET gate, causing a gate heating effect that results in a threshold voltage shift.Type: GrantFiled: May 27, 2005Date of Patent: November 25, 2008Assignee: Agere Systems Inc.Inventor: Edward B. Harris
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Patent number: 7381607Abstract: An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in one embodiment a planar spiral. A region of the substrate below the inductor are removed to lower the inductive Q factor.Type: GrantFiled: May 19, 2006Date of Patent: June 3, 2008Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Stephen W. Downey
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Publication number: 20080073789Abstract: A chip and a method of fabricating the chip for low cost chip identification circuitry. In one embodiment, a method of manufacturing an integrated circuit includes formation of a multi-level metallization structure including a pad level comprising programming pads. A plurality of active devices are formed on a substrate, and multiple levels of metallization are formed over the active devices, connecting some of the active devices to form programmable circuitry. The programmable circuitry is connected to pairs of programming pads on the bond pad level. Programming pads in some of the pairs are selectively connected to one another by using conductive ink deposited with maskless inkjet printing techniques. The pads are then covered with a non-conductive protective layer.Type: ApplicationFiled: September 27, 2006Publication date: March 27, 2008Inventor: Edward B. Harris
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Publication number: 20080072205Abstract: Methods and apparatus are provided for designing a logic circuit using one or more circuit elements having a substantially continuous range of values. A circuit is designed based on a functional description of the circuit and one or more circuit constraints. The circuit is initially designed using a library of discrete circuit element options. The initial circuit design is evaluated to determine whether one or more discrete circuit elements cause the circuit to not satisfy the one or more circuit constraints, such as power, area or timing requirements for the circuit. At least one replacement circuit element is generated that has at least one cell parameter configured such that the at least one replacement circuit element will have a performance characteristic that allows the circuit to satisfy the one or more circuit constraints.Type: ApplicationFiled: September 18, 2006Publication date: March 20, 2008Inventors: Edward B. Harris, Cynthia C. Lee, Gerard Zaneski
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Patent number: 7332924Abstract: Reliability testing circuitry is built into the wafer or IC package in the form of one or more individual testers that use small-area transistors as DUTs. Stress can be applied to the DUTs in parallel and information about breakdown, wearout or failure can be obtained from the individual testers. Only a few pads are needed to test hundreds and even thousands of the DUTs of the individual testers. Testing of many DUTs may be performed using a simple power supply and a few probes.Type: GrantFiled: November 15, 2005Date of Patent: February 19, 2008Assignee: Agere Systems, Inc.Inventors: Edward B. Harris, Bonnie E. Weir
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Patent number: 7259927Abstract: A hard disk drive comprising a plurality of read/write heads oriented to serially read data from the magnetic media of the disk drive. The head output signals are delayed and combined to provide a time aligned composite signal for determining the value of the data bits read from the disk drive. An improved signal-to-noise ratio is provided according to the teachings of the present invention by combining the signal components from the plurality of heads, as the signal components are added algebraically while the noise components are combined as root mean square values. Thus the overall signal-to-noise ratio is improved, resulting in a greater probability of correctly determining the stored data.Type: GrantFiled: July 14, 2003Date of Patent: August 21, 2007Assignee: Agere Systems, Inc.Inventor: Edward B. Harris
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Patent number: 7075167Abstract: An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in one embodiment a planar spiral. A region of the substrate below the inductor are removed to lower the inductive Q factor.Type: GrantFiled: August 22, 2003Date of Patent: July 11, 2006Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Stephen W. Downey
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Patent number: 7022581Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.Type: GrantFiled: July 8, 2004Date of Patent: April 4, 2006Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Canzhong He, Che Choi Leung, Bruce W. McNeill
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Patent number: 6741147Abstract: A thin film resonator comprising a piezoelectric material and having a controllable or tunable resonant frequency. The resonator is formed on a substrate having a cavity formed therein below the piezoelectric film material. A bending electrode is disposed within the cavity and the application of a voltage between the bending electrode and one of the resonator electrodes, creates an electric field that causes the substrate region to bend. These stresses caused: by the bending are transferred to the thin film resonator, subjecting the piezoelectric film to stresses and thereby changing the resonant properties of the thin film resonator.Type: GrantFiled: September 30, 2002Date of Patent: May 25, 2004Assignee: Agere Systems Inc.Inventor: Edward B. Harris
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Publication number: 20040061573Abstract: A thin film resonator comprising a piezoelectric material and having a controllable or tunable resonant frequency. The resonator is formed on a substrate having a cavity formed therein below the piezoelectric film material. A bending electrode is disposed within the cavity and the application of a voltage between the bending electrode and one of the resonator electrodes, creates an electric field that causes the substrate region to bend. These stresses caused by the bending are transferred to the thin film resonator, subjecting the piezoelectric film to stresses and thereby changing the resonant properties of the thin film resonator.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Inventor: Edward B. Harris
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Patent number: 6576563Abstract: The present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method includes forming a positive relief structure from a material located on a substrate, the step of forming the positive relief structure leaving an unwanted remnant of said material proximate a base of the positive relief structure. The method further includes cleaning the positive relief structure. In addition, the method includes removing the unwanted remnant with a gas containing fluorine and that is substantially free of hydrogen.Type: GrantFiled: October 26, 2001Date of Patent: June 10, 2003Assignee: Agere Systems Inc.Inventors: Stephen W. Downey, Edward B. Harris, Paul B. Murphey
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Patent number: 6570238Abstract: A fuse for use in an integrated circuit includes a dielectric layer into which a trench or void is etched defined by a top opening and a bottom floor. The trench includes at least one undercut which forms an overhang in the dielectric layer partially shielding the bottom floor. A second or barrier layer deposited onto the dielectric layer is interrupted or non-continuous at the undercut. A third, or electrically conductive layer, is electrically continuous over the fuse. A weak spot in the third layer exists in the lack of structural support by the second layer at the interruption. A further weak spot in the third layer exists in the electrical isolation of the conductor layer, i.e. no leakage current through the barrier layer, at the interruption.Type: GrantFiled: October 29, 2001Date of Patent: May 27, 2003Assignee: Agere Systems Inc.Inventors: Frank Y. Hui, Edward B. Harris
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Publication number: 20030092273Abstract: The present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method includes forming a positive relief structure from a material located on a substrate, the step of forming the positive relief structure leaving an unwanted remnant of said material proximate a base of the positive relief structure. The method further includes cleaning the positive relief structure. In addition, the method includes removing the unwanted remnant with a gas containing fluorine and that is substantially free of hydrogen.Type: ApplicationFiled: October 26, 2001Publication date: May 15, 2003Applicant: Agere Systems Guardian CorporationInventors: Stephen W. Downey, Edward B. Harris, Paul B. Murphey
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Publication number: 20020070393Abstract: A fuse for use in an integrated circuit includes a dielectric layer into which a trench or void is etched defined by a top opening and a bottom floor. The trench includes at least one undercut which forms an overhang in the dielectric layer partially shielding the bottom floor. A second or barrier layer deposited onto the dielectric layer is interrupted or non-continuous at the undercut. A third, or electrically conductive layer, is electrically continuous over the fuse. A weak spot in the third layer exists in the lack of structural support by the second layer at the interruption. A further weak spot in the third layer exists in the electrical isolation of the conductor layer, i.e. no leakage current through the barrier layer, at the interruption.Type: ApplicationFiled: October 29, 2001Publication date: June 13, 2002Applicant: Agere Systems Guardian Corp.Inventors: Frank Y. Hui, Edward B. Harris
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Patent number: 6323111Abstract: A fuse for use in an integrated circuit includes a dielectric layer into which a trench or void is etched defined by a top opening and a bottom floor. The trench includes at least one undercut which forms an overhang in the dielectric layer partially shielding the bottom floor. A second or barrier layer deposited onto the dielectric layer is interrupted or non-continuous at the undercut. A third, or electrically conductive layer, is electrically continuous over the fuse. A weak spot in the third layer exists in the lack of structural support by the second layer at the interruption. A further weak spot in the third layer exists in the electrical isolation of the conductor layer, i.e. no leakage current through the barrier layer, at the interruption.Type: GrantFiled: October 28, 1999Date of Patent: November 27, 2001Assignee: Agere Systems Guardian CorpInventors: Frank Y. Hui, Edward B. Harris