Patents by Inventor Edward C. Cooney
Edward C. Cooney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10224276Abstract: Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.Type: GrantFiled: October 18, 2017Date of Patent: March 5, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Robert K. Leidy
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Patent number: 10163697Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.Type: GrantFiled: April 4, 2017Date of Patent: December 25, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
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Patent number: 10141274Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.Type: GrantFiled: October 31, 2017Date of Patent: November 27, 2018Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
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Patent number: 10056306Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.Type: GrantFiled: February 4, 2016Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Edward C. Cooney, III, Gary L. Milo, Thomas W. Weeks, Patrick S. Spinney, John C. Hall, Brian P. Conchieri, Brett T. Cucci, Thomas C. Lee
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Publication number: 20180053734Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.Type: ApplicationFiled: October 31, 2017Publication date: February 22, 2018Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
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Patent number: 9893023Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.Type: GrantFiled: May 26, 2017Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
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Publication number: 20180040556Abstract: Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.Type: ApplicationFiled: October 18, 2017Publication date: February 8, 2018Inventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Robert K. Leidy
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Patent number: 9831122Abstract: An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.Type: GrantFiled: May 29, 2012Date of Patent: November 28, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Robert K. Leidy
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Publication number: 20170323855Abstract: Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.Type: ApplicationFiled: May 12, 2017Publication date: November 9, 2017Inventors: Anthony K. Stamper, Edward C. Cooney, III, Laurie M. Krywanczyk
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Publication number: 20170263574Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.Type: ApplicationFiled: May 26, 2017Publication date: September 14, 2017Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
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Publication number: 20170229358Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.Type: ApplicationFiled: February 4, 2016Publication date: August 10, 2017Inventors: Edward C. Cooney, III, Gary L. Milo, Thomas W. Weeks, Patrick S. Spinney, John C. Hall, Brian P. Conchieri, Brett T. Cucci, Thomas C. Lee
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Patent number: 9728509Abstract: Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.Type: GrantFiled: May 5, 2016Date of Patent: August 8, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Anthony K. Stamper, Edward C. Cooney, III, Laurie M. Krywanczyk
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Publication number: 20170207121Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.Type: ApplicationFiled: April 4, 2017Publication date: July 20, 2017Applicant: GlobalFoundries Inc.Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
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Patent number: 9711464Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.Type: GrantFiled: September 23, 2015Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
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Patent number: 9673091Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.Type: GrantFiled: June 25, 2015Date of Patent: June 6, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
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Publication number: 20170084552Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.Type: ApplicationFiled: September 23, 2015Publication date: March 23, 2017Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
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Patent number: 9577023Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.Type: GrantFiled: June 4, 2013Date of Patent: February 21, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Edward C. Cooney, III, Dinh Dang, David A. DeMuynck, Sarah A. McTaggart, Gary L. Milo, Melissa J. Roma, Jeffrey L. Thompson, Thomas W. Weeks
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Publication number: 20160379878Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.Type: ApplicationFiled: June 25, 2015Publication date: December 29, 2016Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
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Patent number: 9355936Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.Type: GrantFiled: April 1, 2014Date of Patent: May 31, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Edward C. Cooney, III, James S. Dunn, Dale W. Martin, Charles S. Musante, BethAnn Rainey Lawrence, Leathen Shi, Edmund J. Sprogis, Cornelia K. Tsang
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Patent number: 9196592Abstract: Various embodiments include managing metal densities in kerf sections of an integrated circuit (IC) wafer. In some embodiments, a method includes: forming an integrated circuit (IC) wafer including a wafer kerf region, the wafer kerf region having a metal density of less than approximately 0.5 percent relative to a total density of the wafer kerf region.Type: GrantFiled: January 10, 2014Date of Patent: November 24, 2015Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Jeffrey P. Gambino, Richard S. Graf, Gary L. Milo