Patents by Inventor Edward Colles Nevill

Edward Colles Nevill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Storing stack operands in registers
    Publication number: 20020066004
    Abstract: A data processing apparatus (102) includes a processor core (104) having a bank of registers (106). The bank of registers (106) include a set of registers that are used for the storage of stack operands. Instructions from a second instruction set specifying stack operands are translated by an instruction translator (108) into instructions of a first instruction set (or control signals corresponding to those instructions) specifying register operands. These translated instructions are then executed by the processor core (104). The instruction translator (108) has multiple mapping states for controlling which registers corresponding to which stack operands within the stack. Changes between mapping states are carried out in dependence of stack operands being added to or removed from the set of registers.
    Type: Application
    Filed: June 25, 2001
    Publication date: May 30, 2002
    Inventors: Edward Colles Nevill, Andrew Christopher Rose
  • Interoperability with multiple instruction sets
    Patent number: 6021265
    Abstract: Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register for indicating the address of a next program instruction word in the data memory; means for modifying the contents of the program counter register in response to a current program instruction word; and control means, responsive to one or more predetermined indicator bits of the program counter register, for controlling the processor core to execute program instruction words of a current instruction set selected from the predetermined plurality of instruction sets and specified by the state of the one or more indicator bits of the program counter register.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: February 1, 2000
    Assignee: ARM Limited
    Inventor: Edward Colles Nevill
  • Interoperability with multiple instruction sets
    Patent number: 5758115
    Abstract: Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register for indicating the address of a next program instruction word in the data memory; means for modifying the contents of the program counter register in response to a current program instruction word; and control means, responsive to one or more predetermined indicator bits of the program counter register, for controlling the processor core to execute program instruction words of a current instruction set selected from the predetermined plurality of instruction sets and specified by the state of the one or more indicator bits of the program counter register.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 26, 1998
    Assignee: Advanced Risc Machines Limited
    Inventor: Edward Colles Nevill