Patents by Inventor Edward Cooney
Edward Cooney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7704876Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.Type: GrantFiled: August 30, 2007Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Jeffrey Gambino, Edward Cooney, III, Anthony Stamper, William Thomas Motsiff, Michael Lane, Andrew Simon
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Publication number: 20080038915Abstract: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.Type: ApplicationFiled: August 31, 2007Publication date: February 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel EDELSTEIN, Matthew COLBURN, Edward COONEY, Timothy DALTON, John FITZSIMMONS, Jeffrey GAMBINO, Elbert HUANG, Michael LANE, Vincent MCGAHAY, Lee NICHOLSON, Satyanarayana NITTA, Sampath PURUSHOTHAMAN, Sujatha SANKARAN, Thomas SHAW, Andrew SIMON, Anthony STAMPER
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Publication number: 20080038923Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.Type: ApplicationFiled: September 6, 2007Publication date: February 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel EDELSTEIN, Matthew COLBURN, Edward COONEY, Timothy DALTON, John FITZSIMMONS, Jeffrey GAMBINO, Elbert HUANG, Michael LANE, Vincent MCGAHAY, Lee NICHOLSON, Satyanarayana NITTA, Sampath PURUSHOTHAMAN, Sujatha SANKARAN, Thomas SHAW, Andrew SIMON, Anthony STAMPER
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Publication number: 20080026566Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.Type: ApplicationFiled: August 30, 2007Publication date: January 31, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey Gambino, Edward Cooney, Anthony Stamper, William Motsiff, Michael Lane, Andrew Simon
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Publication number: 20080020546Abstract: The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.Type: ApplicationFiled: September 27, 2007Publication date: January 24, 2008Applicant: International Business Machines CorporationInventors: Edward COONEY, Vincent McGahay, Thomas Shaw, Anthony Stamper, Matthew Colburn
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Publication number: 20080020230Abstract: Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.Type: ApplicationFiled: October 1, 2007Publication date: January 24, 2008Inventors: Daniel Edelstein, Edward Cooney, John Fitzsimmons, Jeffrey Gambino, Anthony Stamper
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Publication number: 20070275565Abstract: A method and structure for semiconductor structure includes a plurality of adjacent wiring levels, conductors within each of the wiring levels, and liners at least partially surrounding each of the conductors. The liners of adjacent wiring levels are made of different materials which have different etching characteristics and are selectively etchable with respect to one another. The liners can be tantalum, tungsten, etc. The liners surround at least three sides of the conductors. Each of the wiring levels has a first insulator layer which has a first dielectric material. The liners and the conductors are positioned within the first dielectric material. A second insulator layer has a second dielectric material over the first insulator layer. The first dielectric material has a lower dielectric constant than the second dielectric material. The first dielectric material can be silicon dioxide, fluorinated silicon dioxide (FSD), microporous glasses, etc.Type: ApplicationFiled: August 15, 2007Publication date: November 29, 2007Inventors: Edward Cooney, Robert Geffken, Vincent McGahay, William Motsiff, Mark Murray, Amanda Piper, Anthony Stamper, David Thomas, Elizabeth Webster
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Patent number: 7300867Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.Type: GrantFiled: July 5, 2005Date of Patent: November 27, 2007Assignee: International Business Machines CorporationInventors: Jeffrey Gambino, Edward Cooney, III, Anthony Stamper, William Thomas Motsiff, Michael Lane, Andrew Simon
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Publication number: 20070155164Abstract: A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.Type: ApplicationFiled: March 16, 2007Publication date: July 5, 2007Inventors: Steven Barkyoumb, Jonathan Chapple-Sokol, Edward Cooney, Keith Downes, Thomas McDevitt, William Murphy
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Publication number: 20060027929Abstract: Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed-pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant Into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.Type: ApplicationFiled: October 11, 2005Publication date: February 9, 2006Inventors: Edward Cooney, John Fitzsimmons, Jeffrey Gambino, Stephen Luce, Thomas McDevitt, Lee Nicholson, Anthony Stamper
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Publication number: 20060027930Abstract: Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.Type: ApplicationFiled: August 5, 2004Publication date: February 9, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Edelstein, Edward Cooney, III, John Fitzsimmons, Jeffrey Gambino, Anthony Stamper
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Publication number: 20050277266Abstract: The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.Type: ApplicationFiled: June 14, 2004Publication date: December 15, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward Cooney, Vincent McGahay, Thomas Shaw, Anthony Stamper, Matthew Colburn
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Publication number: 20050266698Abstract: Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.Type: ApplicationFiled: May 26, 2004Publication date: December 1, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward Cooney, John Fitzsimmons, Jeffrey Gambino, Stephen Luce, Thomas McDevitt, Lee Nicholson, Anthony Stamper
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Publication number: 20050253265Abstract: A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.Type: ApplicationFiled: May 13, 2004Publication date: November 17, 2005Applicant: International Business Machines CorporationInventors: Steven Barkyoumb, Jonathan Chapple-Sokol, Edward Cooney, Keith Downes, Thomas McDevitt, William Murphy
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Publication number: 20050245068Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.Type: ApplicationFiled: July 5, 2005Publication date: November 3, 2005Applicant: International Business Machines CorporationInventors: Jeffrey Gambino, Edward Cooney, Anthony Stamper, William Motsiff, Michael Lane, Andrew Simon
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Publication number: 20050245098Abstract: A method for selectively altering dielectric properties of a semi-conductor device. In an exemplary embodiment, the method includes applying energy to a local region of interest, the local region of interest including a thermally alterable dielectric such that said heating caused by the applied energy causes a dielectric constant of the thermally alterable dielectric to change.Type: ApplicationFiled: April 28, 2004Publication date: November 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward Cooney, William Motsiff
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Patent number: 6958540Abstract: Interconnect structures are disclosed for forming dual damascene back-end-of-line (BEOL) structure using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.Type: GrantFiled: June 23, 2003Date of Patent: October 25, 2005Assignee: International Business Machines CorporationInventors: Jeffrey Gambino, Edward Cooney, III, Anthony Stamper, William Thomas Motsiff, Michael Lane, Andrew Simon
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Publication number: 20050167838Abstract: A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column.Type: ApplicationFiled: January 30, 2004Publication date: August 4, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Edelstein, Matthew Colburn, Edward Cooney, Timothy Dalton, John Fitzsimmons, Jeffrey Gambino, Elbert Huang, Michael Lane, Vincent McGahay, Lee Nicholson, Satyanarayana Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas Shaw, Andrew Simon, Anthony Stamper
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Publication number: 20050146040Abstract: A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.Type: ApplicationFiled: February 8, 2005Publication date: July 7, 2005Inventors: Edward Cooney, Robert Geffken, Anthony Stamper
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Publication number: 20050085064Abstract: A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias.Type: ApplicationFiled: November 9, 2004Publication date: April 21, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward Cooney, Robert Geffken, Anthony Stamper