Patents by Inventor Edward C. Ross
Edward C. Ross has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11938376Abstract: The present disclosure generally relates to sharing workout content on electronic devices.Type: GrantFiled: May 13, 2022Date of Patent: March 26, 2024Assignee: Apple Inc.Inventors: Anthony D'Auria, Julie A. Arney, Jae Woo Chang, Edward Chao, Nathan De Vries, Michael D. Ford, Colin G. McKinstry, Rex C. Ross
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Patent number: 9094294Abstract: Method and system for reporting out-of-credit condition for a network device connected to a network. An indication to an out-of credit logic is provided that a first sub-port operating using a first protocol is out of credit to transmit information from a transmit segment. The first sub-port is a part of a base-port that includes a plurality of sub-ports that can be configured to operate at more than one operating speed to process packets complying with different protocols. The out-of-credit logic determines when the first sub-port is out-of-credit for a threshold period of time, and reports that the sub-port is out-of-credit to a processor of the network device.Type: GrantFiled: November 15, 2012Date of Patent: July 28, 2015Assignee: QLOGIC, CorporationInventors: Frank R. Dropps, Bret E. Indrelee, Leo J. Slechta, Jr., Gary M. Papenfuss, Edward C. Ross
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Patent number: 8873546Abstract: Method and system for a network switch element is provided. The switch element includes a plurality of megaports, each megaport uniquely identified by a unique megaport address identifier for network addressing. Each megaport includes a plurality of operational ports, each operational port identified by a unique operational port address identifier. The switch element also includes a local crossbar for communication between the plurality of operational ports, and a shared logic module configured to provide common control of the plurality of operational ports within a megaport to allow operational ports to share resource of a single megaport to route network packets there between. The switch element also includes a global crossbar configured to allow communication between the megaports.Type: GrantFiled: October 13, 2011Date of Patent: October 28, 2014Assignee: QLOGIC, CorporationInventors: James A. Kunz, Frank R. Dropps, Edward C. Ross, Mark A. Owen, Craig M. Verba
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Patent number: 8644317Abstract: A fiber channel switch element and method for routing fiber channel frames is provided. The switch element includes a receive segment that can add a virtual storage area network (“VSAN”) tagging header to frames that are received by the receive segment; and strip the VSAN tagging header before frames are sent to ports that do not support virtual fabric capability. The receive segment includes a table used for matching fabric extension parameters. An incoming frame's VSAN identity value is compared to a control word entry to generate a value used for routing the incoming frame. The table is used to determine if a frame is part of a virtual fabric. The routing table for each port is used to route frames and the routing table includes entries for supported virtual fabrics.Type: GrantFiled: July 6, 2011Date of Patent: February 4, 2014Assignee: QLOGIC, CorporationInventors: Frank R. Dropps, Craig M. Verba, Gary M. Papenfuss, Ernest G. Kohlwey, Edward C. Ross
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Patent number: 8200473Abstract: Method and system for processing a management operation command received from a management entity is provided. The management operation command is received by an emulation module for a switch element operationally coupled to the management entity. The switch element includes a plurality of ports, each port having a plurality of components designated as managements devices. The emulation module determines if identification information for a management device in the command matches with identification information stored by the switch element to emulate the management device. If the information matches, then the management operation identified in the management operation command is performed by the emulation module interfacing with a switch element processor.Type: GrantFiled: August 25, 2009Date of Patent: June 12, 2012Assignee: QLOGIC, CorporationInventors: Frank R. Dropps, Edward C. Ross
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Publication number: 20120069839Abstract: Method and system for a network switch element is provided. The switch element includes a plurality of megaports, each megaport uniquely identified by a unique megaport address identifier for network addressing. Each megaport includes a plurality of operational ports, each operational port identified by a unique operational port address identifier. The switch element also includes a local crossbar for communication between the plurality of operational ports, and a shared logic module configured to provide common control of the plurality of operational ports within a megaport to allow operational ports to share resource of a single megaport to route network packets there between. The switch element also includes a global crossbar configured to allow communication between the megaports.Type: ApplicationFiled: October 13, 2011Publication date: March 22, 2012Applicant: QLOGIC, CorporationInventors: James A. Kunz, Frank R. Dropps, Edward C. Ross, Mark A. Owen, Craig M. Verba
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Patent number: 8081650Abstract: A method for assigning virtual lanes (VL) in a fiber channel switch is provided. The fiber channel switch element includes a virtual lane cache that can compare incoming frame parameters based on which virtual lanes may be assigned; and a register to store parameters used for virtual lane assignment. The method includes, determining if VL assignment is to be based on an incoming frame parameter or a programmed value; determining if an incoming frame is a preferred frame; and assigning a preferred routing priority if the incoming frame is designated as a preferred frame. The method also includes, determining if a fabric topology is known; and assigning virtual lanes based on a known fabric topology.Type: GrantFiled: April 22, 2009Date of Patent: December 20, 2011Assignee: QLOGIC, CorporationInventors: Frank R. Dropps, Edward C. Ross, William J Gustafson
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Patent number: 8072988Abstract: A method and system for distributing credit using a fiber channel switch element is provided. The switch element includes, a wait threshold counter that is used to set up a status for a port that has to wait for certain duration to send a frame due to lack of buffer to buffer credit; a credit module that controls buffer to buffer credit for a transmit segment of the fiber channel switch element; and a virtual lane credit module with a counter that is incremented every time a frame assigned to a virtual lane is sent and decreased every time a VC_RDY is received. The method includes, determining if a VC_RDY primitive is received; and allocating credit to a virtual lane that is not at its maximum credit, after the VC_RDY primitive is received.Type: GrantFiled: October 15, 2009Date of Patent: December 6, 2011Assignee: QLOGIC, CorporationInventors: Frank R Dropps, Ernest G Kohlwey, Edward C. Ross, Mark A. Owen
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Patent number: 8068482Abstract: Method and system for a network switch element is provided. The switch element includes a plurality of megaports, each megaport uniquely identified by a unique megaport address identifier for network addressing. Each megaport includes a plurality of operational ports, each operational port identified by a unique operational port address identifier. The switch element also includes a local crossbar for communication between the plurality of operational ports, and a shared logic module configured to provide common control of the plurality of operational ports within a megaport to allow operational ports to share resource of a single megaport to route network packets there between. The switch element also includes a global crossbar configured to allow communication between the megaports.Type: GrantFiled: September 9, 2009Date of Patent: November 29, 2011Assignee: QLOGIC, CorporationInventors: James A. Kunz, Frank R. Dropps, Edward C. Ross, Mark A. Owen, Craig M. Verba
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Patent number: 8006837Abstract: An improved long box package for prerecorded media includes an elongated substantially rectangular box enclosure having a front wall, a rear wall, and a pair of first and second side walls. The box enclosure further includes an open top end, a bottom end adapted to be closed, and an interior shelf disposed between the top end and the bottom end for supporting the bottom end of a media case to be carried by the package. An opening is formed in the front wall that is contiguous with the open top end and which extends toward the shelf. In combination, the open top end and the contiguous front wall opening define an open channel for receiving the media case. The open channel facilitates rapid placement of the media case in the package by virtue of the media case not being restricted to insertion through the top end only.Type: GrantFiled: June 17, 2005Date of Patent: August 30, 2011Assignee: Warner Bros. Entertainment Inc.Inventor: Edward C. Ross
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Patent number: 7990975Abstract: A fibre channel switch element and method for routing fibre channel frames is provided. The switch element includes a receive segment that can add a virtual storage area network (“VSAN”) tagging header to frames that are received by the receive segment; and strip the VSAN tagging header before frames are sent to ports that do not support virtual fabric capability. The receive segment includes a table used for matching fabric extension parameters. An incoming frame's VSAN identity value is compared to a control word entry to generate a value used for routing the incoming frame. The table is used to determine if a frame is part of a virtual fabric. The routing table for each port is used to route frames and the routing table includes entries for supported virtual fabrics.Type: GrantFiled: February 1, 2010Date of Patent: August 2, 2011Assignee: QLOGIC, CorporationInventors: Frank R. Dropps, Craig M. Verba, Gary M. Papenfuss, Ernest G. Kohlwey, Edward C. Ross
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Patent number: 7792115Abstract: A fiber channel switch element with an alias cache is provided for routing and filtering frames. The alias cache includes plural entries including a control word having plural fields including an action code for routing frames; an alias word that is compared to incoming frame data using a frame byte compare block; and a bit mask generator for filtering bit combinations from the frame byte compare block; and a depth match block for determining equality between a control word depth field and incoming frame depth field. Frame data comparison is performed on a bit by bit or byte-by-byte basis. An alias cache entry also includes prerequisite data to determine if results of a different entry are to be used to determine an entry match. The action code routes a frame to a processor, discards a frame, sets a status for inspecting a frame or routes a frame based on a standard Fiber Channel addressing scheme.Type: GrantFiled: July 20, 2004Date of Patent: September 7, 2010Assignee: QLOGIC, CorporationInventors: Frank R. Dropps, Edward C. Ross, Steven M. Betker
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Patent number: 7760752Abstract: A method and switch element for assigning priority to pseudo virtual lanes (“PVL”) using a fibre channel switch element is provided. The method includes, assigning received R_RDYs based on a PVL distribution scheme; and determining traffic congestion on a PVL if there is no credit available to transfer frames from the PVL. A minimum bandwidth feature is enabled to avoid lower priority PVLs from getting no credit for transmitting frames; and distributing credit and R_RDYs based on frame age bits, wherein a lower priority PVL gets credit if a frame is waiting in the PVL for a longer duration compared to a higher priority PVL. The switch element includes, a PVL module having credit counters for plural PVLs; and a timer that monitors frame traffic for each PVL lane. If a PVL gets congested, then a state machine adjusts priority of R_RDY distribution scheme of other PVLs to transmit frames.Type: GrantFiled: June 18, 2008Date of Patent: July 20, 2010Assignee: QLOGIC, CorporationInventors: Frank R. Dropps, Edward C. Ross
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Publication number: 20100128607Abstract: A method and system for distributing credit using a fibre channel switch element is provided. The switch element includes, a wait threshold counter that is used to set up a status for a port that has to wait for certain duration to send a frame due to lack of buffer to buffer credit; a credit module that controls buffer to buffer credit for a transmit segment of the fibre channel switch element; and a virtual lane credit module with a counter that is incremented every time a frame assigned to a virtual lane is sent and decreased every time a VC_RDY is received. The method includes, determining if a VC_RDY primitive is received; and allocating credit to a virtual lane that is not at its maximum credit, after the VC_RDY primitive is received.Type: ApplicationFiled: October 15, 2009Publication date: May 27, 2010Inventors: Frank R. Dropps, Ernest G. Kohlwey, Edward C. Ross, Mark A. Owen
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Publication number: 20100118880Abstract: Method and system for a network switch element is provided. The switch element includes a plurality of megaports, each megaport uniquely identified by a unique megaport address identifier for network addressing. Each megaport includes a plurality of operational ports, each operational port identified by a unique operational port address identifier. The switch element also includes a local crossbar for communication between the plurality of operational ports, and a shared logic module configured to provide common control of the plurality of operational ports within a megaport to allow operational ports to share resource of a single megaport to route network packets there between.Type: ApplicationFiled: September 9, 2009Publication date: May 13, 2010Inventors: James A. Kunz, Frank R. Dropps, Edward C. Ross, Mark A. Owen, Craig M. Verba
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Patent number: 7684401Abstract: A fiber channel switch element and method for routing fiber channel frames is provided. The switch element includes a receive segment that can add a virtual storage area network (“VSAN”) tagging header to frames that are received by the receive segment; and strip the VSAN tagging header before frames are sent to ports that do not support virtual fabric capability. The receive segment includes a table used for matching fabric extension parameters. An incoming frame's VSAN identity value is compared to a control word entry to generate a value used for routing the incoming frame. The table is used to determine if a frame is part of a virtual fabric. The routing table for each port is used to route frames and the routing table includes entries for supported virtual fabrics.Type: GrantFiled: July 20, 2004Date of Patent: March 23, 2010Assignee: QLOGIC, CorporationInventors: Frank R. Dropps, Craig M. Verba, Gary M. Papenfuss, Ernest G. Kohlwey, Edward C. Ross
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Publication number: 20090316592Abstract: A method for assigning virtual lanes (VL) in a fibre channel switch is provided. The fibre channel switch element includes a virtual lane cache that can compare incoming frame parameters based on which virtual lanes may be assigned; and a register to store parameters used for virtual lane assignment. The method includes, determining if VL assignment is to be based on an incoming frame parameter or a programmed value; determining if an incoming frame is a preferred frame; and assigning a preferred routing priority if the incoming frame is designated as a preferred frame. The method also includes, determining if a fabric topology is known; and assigning virtual lanes based on a known fabric topology.Type: ApplicationFiled: April 22, 2009Publication date: December 24, 2009Inventors: Frank R. Dropps, Edward C. Ross, William J. Gustafson
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Patent number: 7630384Abstract: A method and system for distributing credit using a fiber channel switch element is provided. The switch element includes, a wait threshold counter that is used to set up a status for a port that has to wait for certain duration to send a frame due to lack of buffer to buffer credit; a credit module that controls buffer to buffer credit for a transmit segment of the fiber channel switch element; and a virtual lane credit module with a counter that is incremented every time a frame assigned to a virtual lane is sent and decreased every time a VC_RDY is received. The method includes, determining if a VC_RDY primitive is received; and allocating credit to a virtual lane that is not at its maximum credit, after the VC_RDY primitive is received.Type: GrantFiled: July 20, 2004Date of Patent: December 8, 2009Assignee: QLOGIC, CorporationInventors: Frank R Dropps, Ernest G Kohlwey, Edward C. Ross, Mark A. Owen
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Patent number: 7613816Abstract: Method and system for processing frames in a Fibre Channel network is provided. The method includes receiving a frame at a receive port; determining if a translation cache is enabled; determining if there is a match between a received frame header and an entry in the translation cache; generating an encapsulation signal, a de-encapsulation signal, a translation signal or a routing signal; removing data words in the received frame header, if de-encapsulation signal is set; translating the received frame header, if the translation signal is set; encapsulating the frame with an encapsulation header, if the encapsulation signal is set; and routing the frame using translation cache routing if the routing signal is set.Type: GrantFiled: November 15, 2006Date of Patent: November 3, 2009Assignee: QLOGIC, CorporationInventors: Frank R Dropps, Edward C Ross, Ernest G Kohlwey, Craig M Verba, Gary M Papenfuss
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Patent number: 7593997Abstract: A Fibre Channel switch element in a Fibre Channel network is provided. The Fibre Channel switch element includes a port that replaces a logical unit number (“LUN”) field value in a FCP_CMND frame. The port includes a LUN Mapping cache for replacing the LUN field value in a FCP_CMND frame. The LUN Mapping cache may also generate a value that is added to or subtracted from the LUN field value in the FCP_CMND frame. A control bit is used to activate LUN Mapping cache for mapping LUN values.Type: GrantFiled: October 1, 2004Date of Patent: September 22, 2009Assignee: QLOGIC, CorporationInventors: Frank R. Dropps, Edward C. Ross, Steven M. Betker